Abstract: An adaptive circuit is used in the process of recovering data from a signal received from a communications channel. This circuit scripts or varies its transfer function in response to a first error signal derived from the received signal. This adaptation results in the device's transfer function settling to a converged state. An auxiliary information recovery circuit receives the recovered data and derives auxiliary information therefrom. To avoid the problem of false state convergence, the auxiliary information circuit provides a second error signal which causes the adaptive device to reinitiate the adaptation process. In the disclosed embodiment, the adaptive circuit is an equalizer and the auxiliary information recovery circuit is one which recovers framing information or is an error correction circuit. The inability of the auxiliary information circuit to function properly is used as an indication of false convergence of the adaptive circuit.

Abstract: A hardware and algorithm synchronizing arrangement comprising a subsystem synchronization interface circuit is disclosed for controlling the testing of multiple interconnected processors. The circuit permits the pausing of one processor to cause the other interconnected processors to pause as well. The circuit enables a synchronized resumption of the interconnected processors operations. Logic circuitry and signaling interconnections control individual and multiple simultaneous pauses and full duplex operation of a plurality of central control facilities.