Abstract: The present invention is directed to a system having a shared processing resource, a plurality of processing modules and a synchronization control module. The shared processing resource is configured to perform processing operations in connection with input data provided by the processing modules, in response to a start indication. Each of the processing modules is configured to perform selected processing operations. At least one of the processing modules is configured to provide input data to the shared processing resource. Each processing module that provides input data is configured to generate a hold indication and to provide the input data to the shared processing resource in response to a synchronization barrier lock. Each processing module is configured to generate a start enable indication. Each processing module that provides input data generates a start enable indication after providing the input data.

Abstract: A system and method for circuitry design verification testing using a structure of interface independent classes to provide for rapid prototyping and design modification while maximizing test code re-use. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class for collecting common routines and pointers to device transactions. One or more configuration transaction classes derived from the system transaction class define transactions between functional models within the simulation subsystem and cause instantiation of the respective functional models. Operations are performed on the functional models via pointers to interface independent transaction classes which define interfaces to the devices. The operations are mapped to the current designs of the functional models by subclasses of the interface independent transaction classes.

Abstract: A system and method for circuitry design verification testing which provides for maximized code re-use without unnecessary allocation of system resources. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class which collects convenience routines and thereby maximizes code re-use. The system transaction class contains pointers to device transaction classes which correspond to each of the functional models in the simulation subsystem, but does not require instantiation of all of the device transaction classes and associated device objects. One or more configuration transaction classes derived from the system transaction class define transactions between selected ones of the functional models within the simulation subsystem. The configuration transaction classes inherit the convenience routines of the system transaction class, but cause instantiation of the respective functional models only when needed for a transaction.

Abstract: The synchronization state of each of a number of concurrently executing tests which interacts with a particular circuit simulation of one or more circuit simulations which collective simulate a circuit is represented and controlled by a respective local synchronization thread (“LST”) of a hub through which each test interacts with each circuit simulation. When in a synchronization state in which a test is permitted to interact with a particular circuit simulation, the LST corresponding to the test prevents the circuit simulation from advancing simulated time by acquisition by the LST of a hold lock on the circuit simulation. The LST releases the hold lock when the synchronization state of the test is a state in which the test cannot interact with the circuit simulation. Each test is permitted to interact with the circuit simulation in a particular state. When each test completes interaction with the circuit simulation, each test enters a barrier mechanism.

Abstract: A system and method for circuitry design verification testing which provides for maximized code re-use without unnecessary allocation of system resources. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class which collects convenience routines and thereby maximizes code re-use. The system transaction class contains pointers to device transaction classes which correspond to each of the functional models in the simulation subsystem, but does not require instantiation of all of the device transaction classes and associated device objects. One or more configuration transaction classes derived from the system transaction class define transactions between selected ones of the functional models within the simulation subsystem. The configuration transaction classes inherit the convenience routines of the system transaction class, but cause instantiation of the respective functional models only when needed for a transaction.

Abstract: The synchronization state of each of a number of concurrently executing tests which interacts with a particular circuit simulation of one or more circuit simulations which collective simulate a circuit is represented and controlled by a respective local synchronization thread ("LST") of a hub through which each test interacts with each circuit simulation. When in a synchronization state in which a test is permitted to interact with a particular circuit simulation, the LST corresponding to the test prevents the circuit simulation from advancing simulated time by acquisition by the LST of a hold lock on the circuit simulation. The LST releases the hold lock when the synchronization state of the test is a state in which the test cannot interact with the circuit simulation. Each test is permitted to interact with the circuit simulation in a particular state. When each test completes interaction with the circuit simulation, each test enters a barrier mechanism.

Abstract: To simulate a bus of a circuit, a number of virtual bus stubs ("VBSs") each post simulated bus signals as a single step and execution of the simulation system which includes such a VBS continues. As a subsequent, separate step, the VBS substantially immediately thereafter reaps a resolved simulated bus state. Synchronization in such a system is achieved by grouping into zones all VBSs which collectively represent the simulated state of a single bus. Each VBS has one of four states, namely, reap running, reap stopped, post running, post stopped. When a VBS posts, it is determined whether any other VBS of the same zone has yet to reap a previously resolved simulated bus state. If such a VBS exists, the posting VBS moves from reap running state to a post stopped state and execution of the simulation system containing the posting VBS is suspended until the last VBS of a zone reaps the previously resolved simulated bus state.

Abstract: Virtual bus stubs, which can be distributed among constituent computers of a computer network, and a central resolver cooperate to simulate a bus which is connected between multiple circuit parts of a simulated circuit. With each simulated cycle of a clock of the bus, the resolver (i) collects data from the virtual bus stubs representing signals driven on the bus by one or more of the circuit parts, (ii) resolves the current simulated state of the bus from the collected data, and (iii) sends data representing the resolved current simulated state of the bus to the virtual bus stubs. As a result, the virtual bus stubs and the resolver collectively accurately simulate the bus connecting the circuit parts. Since each circuit part has access to the simulated state of the bus through a respective virtual bus stub, each circuit part has access to all information regarding the simulated state of simulated circuit which is necessary for the accurate simulation of each circuit part.

Abstract: A base test class is defined in an object-oriented computer program development environment and members of the base test class, i.e., test objects, represent individual test processes in a computer. The base test class defines a number of attributes and member functions which are inherited by test objects including a constructor member function which is performed when a test object is created. Creation of a test object performs substantially all that is required to implement interfaces and protocols (i) for interaction between the test object and simulation systems, (ii) for synchronization of processing of the test object with processing of other test objects and with simulation systems, and (iii) for reservation by the test object of devices of simulation systems. In addition, a base device class defines a number of attributes and member functions which are inherited by device objects. Device objects represent devices of simulation systems which interact with the test process.

Abstract: Collisions in access to a simulated device are avoided by reserving to one of two or more hardware simulation tests the simulated device. Deadlocks involving requests of multiple tests for reservation of devices are prevented by establishing the order in which such requests are served and requiring that a test must first relinquish reservation of all devices prior to reserving additional devices. Thus, when the additional requests are appended to a queue of pending reservation requests, no test whose requests follow the requests of a second test in the queue can reserve a device requested by the second test. In other words, the situation in which each of two or more tests has reserved a device, reservation of which is required by another of the two or more tests, cannot occur. Starvation is prevented by combining the sorted queue of each reservation phase into a sorted "round robin" arrangement.

Abstract: An interface subsystem for use in a system including one or more simulation systems facilitates simulation of one or more simulation models under control of one or more tests. The interface subsystem allows the tests and simulation systems to transfer information therebetween and enables said tests to control the simulation systems in simulating the simulation model during a simulation run. The simulation systems include transactors which provide information to the simulation model at the beginning of a simulation run, pause a simulation run in response to detection of a selected event, and generate simulation result information. The interface subsystem includes, associated with each test, a simulation information generator, a simulation control indicator generator, and a information receiver; associated with each simulation system an information receiver associated with each transactor and a simulator interface module; and an interface core.

Abstract: A fault tolerant computer system is described in which a direct memory access controller examines the check bit data on every data element that is accessed by the system. The address of any data element that is found to have an error in the check bit data is stored by the direct memory access controller, the check bit data is used by the direct memroy access controller to correct the error, and the corrected data element is rewritten to the original storage address. By the use of this arrangement, the central processing unit or units of the computer system are free to perform other tasks, thus improving system throughput, and preventing the accumulation of data element errors in the memory.

Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device.

Abstract: Method and apparatus for controlling initiating of bootstrap loading in a computer system having first and second discrete computing zones is disclosed. Each computing zone includes a status register for storing an operating system run (OSR) bit indicating that the zone has initiated bootstrap loading. A cable connects the computing zones to allow the first and second zones to read the status registers in the second and first zones, respectively. A CPU in each zone only enables initiation of bootstrap loading if the OSR bit in the other zone is not set.