Abstract: A method and apparatus for very low, in some case even zero, data latency accesses to a shared resource for devices such as disk drives and their channel formatting agents. The method and apparatus together will controllably terminate any non-low-latency access in process and then start a low latency access. Since the computer system has a group of three agents that may require low latency accesses, a special low latency arbitration method and apparatus is provided instead of the normal dynamic time loop arbitration. The low latency arbitration is call zero latency loop arbitration. The method and apparatus can actually provide zero latency data accesses for disk reads and writes in many cases. Once all low latency accesses are fulfilled, the method and apparatus allow the computer system to return to its slower, normal dynamic timed loop arbitration.

Abstract: In a computer system where maximum allowable latency periods are established for each of eight agents to access a shared buffer, the invention provides a timed loop that prevents starving out of any agent and a dynamically variable loop to prevent an allocation of time for an access to the shared buffer by an idle agent to reduce latency wherever possible.

Abstract: A synchronizer which samples and stores the synchronized data with a transparent latch instead of a flip-flop or similar device to avoid the long set-up times required by such devices. The synchronizer compares its input level to its output level. When they are found to be different because of an input data change, the difference is used to gate the system clock, which in turn gates the transparent latch to sample and store the changed input data level as the new data output level. Since the change in the input data gates the system clock which further gates the opening of the latch, the input data is essentially guaranteed to fulfill the latch set up time requirements. For the difficult case when the input data change occurs as the clock is changing states, a Schmitt trigger is inserted ahead of the latch gating input. The Schmitt trigger will either respond and provide a proper pulse width and magnitude to drive the latch without metastability, or it will pass a "runt pulse" and not respond to it.

Abstract: A method and apparatus for controlling ground bounce and transient noise induced in an integrated circuits power supply buses by feeding back the input/output power supply bus voltages levels and comparing those levels to the internal logic power supply bus voltage levels. Significant noise transients on the input/output upper potential power supply bus will increase a resistance of a series element in each buffer circuit that drives a respective output driver and thereby increase the overall switching time of each buffer and output driver combination. Similarly, significant ground bounce voltages on the input/output lower potential power supply bus will increase a resistance of another series element in each buffer circuit driving its respective output driver and thereby increase the overall switching time of each buffer and output driver combination.