Abstract: A system and method are disclosed for transmitting upstream data from a cable modem within a cable television plant. One aspect of the invention pertains to a method that includes transmitting a first portion of the upstream data on a first upstream channel from the cable modem and transmitting a second portion of the upstream data on a second upstream channel from the cable modem. The second upstream channel differs from the first upstream channel. In another aspect, the invention pertains to a cable modem that includes a processor configured to initiate transmission on multiple upstream channels. The cable modem further includes an upstream transmitting component operating in conjunction with the processor and configurable by the processor to transmit data over multiple upstream channels.

Abstract: A configuration editor receives requests to access a configuration area for a cable modem. Each configuration area corresponds to a particular user type. The configuration editor can then retrieve configuration data corresponding to the configuration area for the particular user type. An area editor selects data fields corresponding to configuration data, and allocates the data fields to one or more configuration areas corresponding to particular user types.

Abstract: A configuration editor receives requests to access a configuration area for a cable modem. Each configuration area corresponds to a particular user type. The configuration editor can then retrieve configuration data corresponding to the configuration area for the particular user type. An area editor selects data fields corresponding to configuration data, and allocates the data fields to one or more configuration areas corresponding to particular user types.

Abstract: A method and apparatus for reliable interrupt reception over a buffered bus utilizes a mailbox register to receive interrupt request information sent after a data write transaction. The data is sent from an initiating peripheral device over the buffered bus to arrive with an arbitrary delay at the host memory. After completing the sending phase for the data the initiating peripheral device sends a mailbox register data block containing an interrupt request to a mailbox register associated with the host processor. Because the mailbox register data block will necessarily arrive after the receipt of the actual data in the host memory because it is following the actual data through the same buffered bus, the interrupt will be properly sequenced with the receipt of data.

Abstract: A method and apparatus for reliable interrupt reception over a buffered bus utilizes a non-delayed non-posted write transaction to write data over the bus from a peripheral device to host memory. Because there is no buffering delay in a non-delayed non-posted write transaction, at the completion of the write cycle the peripheral knows that the write transaction is complete and then sends an interrupt request to the host processor requesting the host processor to service the interrupt and process the contents of the host memory.