Patents by Inventor Glenn Farrall
Glenn Farrall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10592270Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.Type: GrantFiled: October 16, 2017Date of Patent: March 17, 2020Assignee: Infineon Technologies AGInventors: Simon Brewerton, Glenn Farrall, Neil Hastie, Frank Hellwig, Richard Knight, Antonio Vilela
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Patent number: 10248595Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.Type: GrantFiled: August 10, 2017Date of Patent: April 2, 2019Assignee: Infineon Technologies AGInventors: Frank Hellwig, Gerhard Wirrer, Glenn Farrall, Neil Hastie
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Publication number: 20190050356Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.Type: ApplicationFiled: August 10, 2017Publication date: February 14, 2019Inventors: Frank Hellwig, Gerhard Wirrer, Glenn Farrall, Neil Hastie
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Publication number: 20180039508Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.Type: ApplicationFiled: October 16, 2017Publication date: February 8, 2018Inventors: Simon Brewerton, Glenn Farrall, Neil Hastie, Frank Hellwig, Richard Knight, Antonio Vilela
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Patent number: 9836318Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.Type: GrantFiled: March 12, 2014Date of Patent: December 5, 2017Assignee: Infineon Technologies AGInventors: Simon Brewerton, Glenn Farrall, Neil Hastie, Frank Hellwig, Richard Knight, Antonio Vilela
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Publication number: 20150242233Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.Type: ApplicationFiled: March 12, 2014Publication date: August 27, 2015Inventors: Simon Brewerton, Glenn Farrall, Neil Hastie, Frank Hellwig, Richard Knight, Antonio Vilela
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Patent number: 8880961Abstract: A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.Type: GrantFiled: January 31, 2012Date of Patent: November 4, 2014Assignee: Infineon Technologies AGInventors: Simon Brewerton, Neil Hastie, Glenn Farrall, Boyko Traykov, Antonio Vilela
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Publication number: 20130198571Abstract: A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Applicant: Infineon Technologies AGInventors: Simon Brewerton, Neil Hastie, Glenn Farrall, Boyko Traykov, Antonio Vilela
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Publication number: 20110208948Abstract: Embodiments relate to systems and methods for reading from and writing to interface peripherals or other shared resources during robust computation utilizing temporally separated redundant execution. Embodiments can be utilized in safety-relevant applications related to automotive, banking and finance, aerospace, defense, Internet payment, and others.Type: ApplicationFiled: February 23, 2010Publication date: August 25, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Richard Knight, Neil Hastie, Simon Brewerton, Glenn Farrall
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Patent number: 7793261Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.Type: GrantFiled: October 1, 1999Date of Patent: September 7, 2010Assignee: STMicroelectronics LimitedInventors: David Alan Edwards, Margaret Rose Gearty, Glenn A. Farrall, Atsushi Hasegawa, Anthony Willis Rich
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Patent number: 6546467Abstract: A computer system has a processor, a cache and a main memory. A cache coherency mechanism ensures that the contents of the cache are coherent with respect to main memory by the provision of cache coherency instructions which each specify: 1) an operation to be executed on the contents of a location in the cache; and 2) an address in main memory. The operation is executed for the contents of the location in the cache which could be filled by an access to that address in main memory if the executing process normally has access to that address in main memory, regardless of whether or not the contents of the specified address in main memory are held at that location in the cache. This provides an extra degree of freedom because it is not necessary for the cache coherency operation to be requested in respect of a particular address stored in the cache. The instruction can specify any address which would map onto that cache location.Type: GrantFiled: March 2, 1998Date of Patent: April 8, 2003Assignee: SGS-Thomson Microelectronics LimitedInventors: Glenn Farrall, Bruno Fel, Catherine Barnaby
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Patent number: 6453385Abstract: A cache system and method of operating are described in which a cache is connected between a processor and a main memory of a computer. The cache system includes a cache memory having a set of cache partitions. Each cache partition has a plurality of addressable storage locations for holding items fetched from said main memory for use by the processor. The cache system also includes a cache refill mechanism arranged to fetch an item from the main memory and to load said item into the cache memory at one of said addressable storage locations in a cache partion wich depends on the address of said item in the main memory. This is achieved by a cache partition access table holding in association with addresses of items to be cached respective multi-bit partition indications identifying one or more cache partition into which the item is to be loaded.Type: GrantFiled: January 27, 1998Date of Patent: September 17, 2002Assignee: SGS-Thomson Microelectronics LimitedInventors: Andrew Craig Sturges, David May, Glenn Farrall, Bruno Fel, Catherine Barnaby
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Publication number: 20020007442Abstract: A computer system has a processor, a cache and a main memory. A cache coherency mechanism ensures that the contents of the cache are coherent with respect to main memory by the provision of cache coherency instructions which each specify: 1) an operation to be executed on the contents of a location in the cache; and 2) an address in main memory. The operation is executed for the contents of the location in the cache which could be filled by an access to that address in main memory if the executing process normally has access to that address in main memory, regardless of whether or not the contents of the specified address in main memory are held at that location in the cache.Type: ApplicationFiled: March 2, 1998Publication date: January 17, 2002Inventors: GLENN FARRALL, BRUNO FEL, CATHERINE BARNABY