Abstract: Methods and materials for treating and preventing autoimmune diseases, in particular, multiple sclerosis (MS) including small peptides are capable of interacting with CD40, thereby altering and/or modulating the ability of CD40 to interact with CD154, which apparently affects inflammation; and/or the use of such peptides in reducing the inflammatory response, and in particular, the autoimmune inflammatory response; and/or the use of such short peptides to prevent or reverse autoimmune disease, and particularly, multiple sclerosis, in individuals; and/or methods and materials for detecting T-cells that express CD40 (Th40 cells). Also provided are kits for reducing inflammation, treating autoimmune diseases, or detecting Th40 cells. Additionally, methods and apparatuses to administer the peptide are provided.

Abstract: A method for operating an apparatus that includes a program memory, a data memory and a status register that holds a status, wherein the status has fields including: a program memory address at which a most recent instruction is fetched from the program memory, a data memory access address at which data has most recently been accessed in the data memory by the apparatus and a repeat count indicating a number of times an operation specified in a current program instruction remains to be performed, the apparatus further including a condition register having condition fields corresponding to the status fields held in the status register, the method including: writing the condition register with a condition including the condition fields; and generating an interrupt request to a processing core in response to detecting that the status held in the status register satisfies the condition specified in the condition register.

Abstract: A programmable apparatus includes a program memory that holds instructions of a program fetched and executed by the apparatus, a data memory that holds data processed by the instructions, a status register that holds a status having fields: a program memory address at which a most recent instruction is fetched from the program memory, a data memory access address at which data has most recently been accessed in the data memory by the apparatus and a repeat count that indicates a number of times an operation specified in a current program instruction remains to be performed. A condition register has condition fields corresponding to the status register fields. Control logic generates an interrupt request to a processing core in response to detecting that the status held in the status register satisfies the condition specified in the condition register.

Abstract: An apparatus includes a first memory, processing units that access the first memory, and a counter that, for each period of a sequence of periods, holds an indication of accesses to the first memory during the period; and control logic that, for each period of the sequence of periods, monitors the indication to determine whether it exceeds the threshold and, if so, stalls the processing units from accessing the first memory for a remaining portion of the period.

Abstract: A processor including a memory controller for interfacing an external memory and a programmable functional unit (PFU). The PFU is programmed by a PFU program to modify operation of the memory controller, in which the PFU includes programmable logic elements and programmable interconnectors. For example, the PFU is programmed by the PFU program to add a function or otherwise to modify an existing function of the memory controller enhance its functionality during operation of the processor. In this manner, the functionality and/or operation of the memory controller is not fixed once the processor is manufactured, but instead the memory controller may be modified after manufacture to improve efficiency and/or enhance performance of the processor, such as when executing a corresponding process.

Abstract: A hardware processing unit is provided. The hardware processing unit includes: an accumulator; a multiplier-adder receives first and second factors and receives an addend, the multiplier-adder generates a sum of the addend and a product of the first and second factors and provides the sum; a first multiplexer receives a first operand, a positive one, and a negative one and selects one of them for provision as the first factor to the multiplier-adder; a second multiplexer receives a second operand, a positive one, and a negative one and selects one of them for provision as the second factor to the multiplier-adder; a third multiplexer, having an output, that receives the first operand and the second operand and selects one of them for provision on its output; and a fourth multiplexer receives the third multiplexer output and the sum and selects one of them for provision to the accumulator.

Abstract: A neural network unit includes a register programmable with a control value, a plurality of neural processing units (NPU), and a plurality of activation function units (AFU). Each NPU includes an arithmetic logic unit (ALU) that performs arithmetic and logical operations on a sequence of operands to generate a sequence of results and an accumulator into which the ALU accumulates the sequence of results as an accumulated value. Each AFU includes a first module that performs a first function on the accumulated value to generate a first output, a second module that performs a second function on the accumulated value to generate a second output, the first function is distinct from the second function, and a multiplexer that receives the first and second outputs and selects one of the two outputs based on the control value programmed into the register.

Abstract: A first data storage holds cache lines, an accelerator has a second data storage that selectively holds accelerator data and cache lines evicted from the first data storage, a tag directory holds tags for cache lines stored in the first and second data storages, and a mode indicator indicates whether the second data storage is operating in a first or second mode in which it respectively holds cache lines evicted from the first data storage or accelerator data. In response to a request to evict a cache line from the first data storage, in the first mode the control logic writes the cache line to the second data storage and updates a tag in the tag directory to indicate the cache line is present in the second data storage, and in the second mode the control logic instead writes the cache line to a system memory.

Abstract: A neural network unit has a first memory that holds elements of a data matrix and a second memory that holds elements of a convolution kernel. An array of neural processing units (NPU) each have a multiplexed register that receives a corresponding element of a row from the first memory and that also receives the multiplexed register output of an adjacent NPU. A register receives a corresponding element of a row from the second memory. An arithmetic unit receives the outputs of the register, the multiplexed register and an accumulator and performs a multiply-accumulate operation on them. For each sub-matrix of a plurality of sub-matrices of the data matrix, each arithmetic unit selectively receives either the element from the first memory or the adjacent NPU multiplexed register output and performs a series of the multiply-accumulate operations to accumulate into the accumulator a convolution of the sub-matrix with the convolution kernel.

Abstract: A processor comprising a mode indicator, a plurality of processing cores, and a neural network unit (NNU), comprising a memory array, an array of neural processing units (NPU), cache control logic, and selection logic that selectively couples the plurality of NPUs and the cache control logic to the memory array. When the mode indicator indicates a first mode, the selection logic enables the plurality of NPUs to read neural network weights from the memory array to perform computations using the weights. When the mode indicator indicates a second mode, the selection logic enables the plurality of processing cores to access the memory array through the cache control logic as a cache memory.

Abstract: A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.

Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

Abstract: A processor includes a front-end portion that issues instructions to execution units that execute the issued instructions. A hardware neural network unit (NNU) execution unit includes a first memory that holds data words associated with artificial neural networks (ANN) neuron outputs, a second memory that holds weight words associated with connections between ANN neurons, and a third memory that holds a program comprising NNU instructions that are distinct, with respect to their instruction set, from the instructions issued to the NNU by the front-end portion of the processor. The program performs ANN-associated computations on the data and weight words. A first instruction instructs the NNU to transfer NNU instructions of the program from architectural general purpose registers to the third memory. A second instruction instructs the NNU to invoke the program stored in the third memory.

Abstract: A memory holds D rows of N words and receives an address having log2 D bits and an extra bit. Each of N processing units (PU) of index J has first and second registers, an accumulator, an arithmetic unit that performs an operation thereon to accumulate a result, and multiplexing logic receiving memory word J, and for PUs 0 to (N/2)?1 also memory word J+(N/2). In a first mode, the multiplexing logic of PUs 0 to N?1 selects word J to output to the first register. In a second mode: when the extra bit is a zero, the multiplexing logic of PUs 0 to (N/2)?1 selects word J to output to the first register, and when the extra bit is a one, the multiplexing logic of PUs 0 through (N/2)?1 selects word J+(N/2) to output to the first register.

Abstract: First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J?1 and outputs a selected data word to the register. PU J?1 for PU 0 is PU N?1. The multiplexing logic of PU 0 also receives the data word output by the register of PU (N/2)?1. The multiplexing logic of PU N/2 also receives the data word output by the register of PU N?1.

Abstract: First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J?1 and outputs a selected data word to the register. PU J?1 for PU 0 is PU N?1. The multiplexing logic of PU N/4 also receives the data word output by the register of PU (3N/4)?1. The multiplexing logic of PU 3N/4 also receives the data word output by the register of PU (N/4)?1.

Abstract: A neural network unit has at least one RAM, an output buffer and an array of neural processing units that: read first time step context layer node values from the output buffer; read second time step input layer node values from the RAM; generate second time step hidden layer node values based on the read input and context layer node values; output the hidden layer node values to the output buffer rather than to the RAM; read the hidden layer node values from the output buffer; generate second time step context layer node values based on the read hidden layer node values; output the context layer node values to the output buffer rather than to the RAM; generate output layer node values using the hidden layer node values; write the output layer node values to the RAM; and repeat for a sequence of time steps.

Abstract: In a neural network unit, each neural processing unit (NPU) of an array of N NPUs receives respective first and second upper and lower bytes of 2N bytes received from first and second RAMs. In a first mode, each NPU sign-extends the first upper byte to form a first 16-bit word and performs an arithmetic operation on the first 16-bit word and a second 16-bit word formed by the second upper and lower bytes. In a second mode, each NPU sign-extends the first lower byte to form a third 16-bit word and performs the arithmetic operation on the third 16-bit word and the second 16-bit word formed by the second upper and lower bytes. In a third mode, each NPU performs the arithmetic operation on a fourth 16-bit word formed by the first upper and lower bytes and the second 16-bit word formed by the second upper and lower bytes.

Abstract: A neural network unit includes a programmable indicator, a first memory that holds first operands, a second memory that holds second operands, neural processing units (NPU), and activation units. Each NPU has an accumulator and an arithmetic unit that performs a series of multiply operations on pairs of the first and second operands received from the first and second memories to generate a series of products, and a series of addition operations on the series of products to accumulate an accumulated value in the accumulator. The activation units perform activation functions on the accumulated values in the accumulators to generate results. When the indicator specifies the first action, the neural network unit writes to the first memory the results generated by the activation units. When the indicator specifies the second action, the neural network unit writes to the first memory the accumulated values in the accumulators.

Abstract: An array of N processing units (PU) each has: an accumulator; an arithmetic unit performs an operation on first, second and third inputs to generate a result to store in the accumulator, the first input receives the accumulator output; a weight input is received by the second input to the arithmetic unit; a multiplexed register has first and second data inputs, an output received by the third input to the arithmetic unit, and a control input that controls the data input selection. The multiplexed register output is also received by an adjacent PU's multiplexed register second data input. The N PU's multiplexed registers collectively operate as an N-word rotater when the control input specifies the second data input. Respective first/second memories hold W/D rows of N weight/data words and provide the N weight/data words to the corresponding weight/multiplexed register first data inputs of the N PUs.