Abstract: A method and apparatus for dispatching load operations in a computer system. The present invention includes a method and apparatus for determining when the load operation is ready for dispatched to memory. The load operation is then scheduled to dispatch from memory and then dispatched to memory. In the present invention, a load is determined ready when it is no longer blocked, such that there is no condition which produces a resource or address dependency causing the load to be blocked.

Abstract: A method and apparatus for binding instructions to dispatch ports in a reservation station includes a counter mechanism and a port identifier. The counter mechanism maintains a count of instructions which are pending dispatch from at least one of the dispatch ports. The port identifier receives an instruction and identifies to which of the dispatch ports the instruction is to be bound, based on the count of instructions maintained by the counter mechanism.

Abstract: A method and apparatus for instruction refetch in a processor is provided. To ensure that a macro instruction is available for refetching after the processor has handled an event or determined a correct restart address after a branch misprediction, an instruction memory includes an instruction cache for caching macro instructions to be fetched, and a victim cache for caching victims from the instruction cache. To ensure the availability of a macro instruction for refetching, the instruction memory (the instruction cache and victim cache together) always stores a macro instruction that may need to be refetched until the macro instruction is committed to architectural state. A marker micro instruction is inserted into the processor pipeline when an instruction cache line is victimized. The marker specifies an entry in the victim cache occupied by the victimized cache line.

Abstract: A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress.

Abstract: A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress.

Abstract: A method and apparatus for performing store operations that includes calculating the address and obtaining the data for the store operation. The address represents the memory location to which the data is to be stored. Once the address is calculated and the data obtained, the store operation is committed to processor state. The store operation may be dispatched to memory to complete the execution of the store operation.

Abstract: A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.

Abstract: A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.

Abstract: Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.

Abstract: A translation lookaside buffer is described for use with a microprocessor capable of speculative and out-of-order processing of memory instructions. The translation lookaside buffer is non-blocking in response to translation lookaside buffer misses requiring page table walks. Once a translation lookaside buffer miss is detected, a page table walk is initiated to satisfy the miss. During the page table walk, additional memory instructions are processed by the translation lookaside buffer. Any additional instructions which cause translation lookaside buffer hits are merely processed by the translation lookaside buffer. However, instructions causing translation lookaside buffer misses while the page table walk is being performed are blocked pending completion of the page table walk. Once the page table walk is completed the blocked instructions are reawakened and are again processed by the translation lookaside buffer. Global and selective wakeup mechanisms are described.

Abstract: A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.

Abstract: Store forwarding circuitry is provided to an out-of-order execution processor having a store buffer of buffered memory store operations. The store forwarding circuitry conditionally forwards store data for a memory load operation from a variable subset of the buffered memory store operations that is functionally dependent on the time the memory load operation is issued, taking into account the execution states of these buffered memory store operations. The memory load operation may be issued speculatively and/or executed out-of-order. The execution states of the buffered memory store operations may be speculatively executed or committed. The data and address aspects of the memory store operations may be executed separately.

Abstract: A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer.

Abstract: Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.

Abstract: A method and apparatus for performing error correction on data from an external memory is described. The present invention includes a method and apparatus for receiving data from an external memory source and determining if the data has an error. The data is forwarded to the requesting unit while the error correction is performed on the data, such that the two operations are performed in parallel.The present invention also includes a method and apparatus for subsequently correcting data if a single bit error exists. The corrected data is then forwarded to the requesting unit during the next cycle. Also if an error is detected, the present invention produces an indication to the device. The device is flushed in response to the indication.

Abstract: In an out-of-order execution computer system, a store buffer is conditionally signaled to output buffered store data of buffered memory store operations, when a buffered memory load operation is being executed. The determination on whether to signal the store buffer or not is made using control information that includes the allocation state of the store buffer at the time the memory load operation being executed was issued. The allocation state includes the identification of the buffer slot storing the last memory store operation stored into the store buffer, and the wraparound state of a circular wraparound allocation approach employed to allocate buffer slots to the memory store operations, at the time the memory load operation being executed was issued.

Abstract: A method of state recovery following a branch misprediction or an undetected branch instruction. If, during execution of a branch instruction in an out-of-order unit, it is determined that the branch has been mispredicted, or if a taken branch has not been detected, then a JEClear signal is asserted to flush the instruction fetch unit and decoder section, and to change the instruction pointer to the actual target address. Within the out-of-order section, the instructions preceding the branch instruction are allowed to continue execution and proceed to in-order retirement. Simultaneously, instructions fetched at the actual target address are decoded, but not allowed to issue therefrom until the branch instruction has been retired from the out-of-order section, after which all instructions within the out-of-order section are flushed, and then decoded instructions are allowed to issue from the decoder. The state recovery method advantageously provides efficient utilization of processor time.

Abstract: A branch prediction mechanism that maintains both speculative history and actual history for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history plus the "history" of recent branch predictions for the branch. If the speculative branch history contains any recent predictions, then a speculation bit is set. When the speculation bit is set, this indicates that there is speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a misprediction is made for the branch, the speculation bit is cleared since the speculative history contains inaccurate branch history.

Abstract: An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries.

Abstract: An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries.