Abstract: In an array of multi-color vertical detector color pixel sensors, a readout wiring architecture includes a transfer transistor for each individual color detector. In first and second rows in a first column, the first, second, and third color transfer transistor gates are coupled, respectively, to the first, second, and third row-select lines. In a first row in a second column, the first color transfer transistor gate is coupled to the second row-select line, the second color transfer transistor gate is coupled to the first row-select line, and the third color transfer transistor gate is coupled to the third row-select line. In a second row in the second column, the first color transfer transistor gate is coupled to the first row-select line, the second color transfer transistor gate is coupled to the third row-select line, and t the third color transfer transistor gate is coupled to the second row-select line.

Abstract: An installation tool for aiding in securing a device within a data center rack, the installation tool includes a plate having a shape appropriate to fit within an interior of the data center rack; a first mount extending from a first front corner of the plate, the first mount having a first peg; and a second mount extending from a second front corner of the plate, the second mount having a second peg; the first and second peg are to secure the first mount and the second mount to a frame of the data center rack; and the plate provides a surface to hold the device within the data center rack for the device to be secured to the data center rack.

Abstract: In an array of multi-color vertical detector color pixel sensors, a readout wiring architecture includes a transfer transistor for each individual color detector. In first and second rows in a first column, the first, second, and third color transfer transistor gates are coupled, respectively, to the first, second, and third row-select lines. In a first row in a second column, the first color transfer transistor gate is coupled to the second row-select line, the second color transfer transistor gate is coupled to the first row-select line, and the third color transfer transistor gate is coupled to the third row-select line. In a second row in the second column, the first color transfer transistor gate is coupled to the first row-select line, the second color transfer transistor gate is coupled to the third row-select line, and t the third color transfer transistor gate is coupled to the second row-select line.

Abstract: In an array containing rows and columns of multi-color vertical detector color pixel sensors disposed in a rows and columns of the array, a readout wiring architecture includes a plurality of row-select lines for each row of the array, equal to the number of colors in the vertical detector color pixel sensors, an individual column line for each column, a transfer transistor for each individual color detector coupled between a color detector and a column line associated with the column in which the color detector is disposed. Each transfer transistor has a gate coupled to one of the plurality of row-select lines in a row in which the vertical detector color pixel sensor is disposed. The gates of at least some of the transfer transistors in each row for each color detector in adjacent columns of the array are coupled to different ones of the row-select lines for that row.

Abstract: In an array containing rows and columns of multi-color vertical detector color pixel sensors disposed in a rows and columns of the array, a readout wiring architecture includes a plurality of row-select lines for each row of the array, equal to the number of colors in the vertical detector color pixel sensors, an individual column line for each column, a transfer transistor for each individual color detector coupled between a color detector and a column line associated with the column in which the color detector is disposed. Each transfer transistor has a gate coupled to one of the plurality of row-select lines in a row in which the vertical detector color pixel sensor is disposed. The gates of at least some of the transfer transistors in each row for each color detector in adjacent columns of the array are coupled to different ones of the row-select lines for that row.

Abstract: A peripheral control circuit for a computer system. Independent control and interface circuits are provided for left and right audio channels, for a communications port, for storage media, and for joysticks or paddles. Control logic is provided for direct memory access to system memory and for interrupts to the processor by each of the peripherals. Sound data corresponding to a sound waveform during a particular time period is fetched using DMA or interrupts. Registers store data for selecting the output rate of the sound data, the length of the sound waveform, and the volume of the sound waveform. Four audio channels and two separate audio ports are provide.

Abstract: A digital phase locked loop circuit for reading input data transmitted from storage media. Counter and adder components establish the time of arrival of input data bits. Inspection windows are established having durations and start/stop times that can be adjusted by correction signals so that subsequent data bits will be received in the middle of the inspection windows. Correction signals to the counter and adder components compensate for variations in the phase and frequency of input data transmitted from storage media.