Abstract: An IC layout tool determines areas of an IC layout in which to provide power wire interconnection vias by first querying a “world” HV tree keeping track of power wires and other objects within the IC layout to determine areas of overlap between power wires residing on differing layers of the layout. The layout tool then creates a separate via HV tree identifying positions of “via boxes” residing on areas of each layer of the IC between overlapping power wires. The tool manipulates the data stored in the via HV tree to partition and merge adjacent via boxes residing on each layer as necessary to produce via boxes indicating positions of a set of unobstructed, rectangular areas of each layer of the layout in which vias may be placed to interconnect overlapping power wires. The IC layout tool then places vias in each rectangular area of each layer the via HV tree indicates is being occupied by via boxes.

Abstract: An IC layout tool determines areas of an IC layout in which to provide power wire interconnection vias by first querying a “world” HV tree keeping track of power wires and other objects within the IC layout to determine areas of overlap between power wires residing on differing layers of the layout. The layout tool then creates a separate via HV tree identifying positions of “via boxes” residing on areas of each layer of the IC between overlapping power wires. The tool manipulates the data stored in the via HV tree to partition and merge adjacent via boxes residing on each layer as necessary to produce via boxes indicating positions of a set of unobstructed, rectangular areas of each layer of the layout in which vias may be placed to interconnect overlapping power wires. The IC layout tool then places vias in each rectangular area of each layer the via HV tree indicates is being occupied by via boxes.