Abstract: A polygon sort engine including first and second apparatus for sorting. The first apparatus for sorting receives planar, externally convex polygon vertices from an external polygon tiling engine. This includes points and lines. The state machine on the second apparatus for sorting interfaces with the polygon tiling engine and a raster engine in a graphics pipeline. It provides a control signal which determines when the first apparatus for sorting will receive the next polygon. The second sorting appartus also controls whether the polygon is stored in the PING or PONG memory. For example, as the state machine is controlling the sorting of the current polygon into the PING RAM, the state machine will also be controlling the loading of the previous vertices and the PONG RAM into the raster engine.

Abstract: A bus interface controller for use in a digital information system. The bus interface comprises more than four bi-directional data channels which are multiplexed so as to accomplish switching of data from any channel to any or all of the remaining channels. The device is preferably embedded in a substate comprising gallium arsenide material and operates at a frequency of at least 25 MHz.