Abstract: An improved asymmetrical data tracking digital phase locked loop including separate baud rate counters for both the positive data pulse edge and the negative data pulse edge. The outputs of the two independent baud rate counters are added together and divided by two in a virtual counter for each local oscillator clock cycle. This provides a data clock pulse located at the midpoint between the corresponding data pulse edges as defined by the two baud rate counters. A digital filter is utilized to dampen the tracking loop correction to reduce maximum phase errors by not allowing continuous phase corrections.