Abstract: A method of accessing information in a cache of a multithreaded system comprises providing a virtual address of an instruction to be accessed by a thread. Upon a cache miss, the physical address of the information is compared with the physical address of an instruction stored in the cache, and if they match, the instruction is accessed from the cache. Alternatively, the cache is searched for an entry having a virtual address which matches the instruction's virtual address, and having some indication of being associated with the accessing thread. Upon finding such an entry, the instruction is accessed from the cache. In addition, the instruction may be accessed from the cache upon finding a cache entry whose virtual address matches the instruction's virtual address, and which either has an address space matching the address space of the thread, or has an indication that the entry matches all address spaces.

Abstract: The outcome of a plurality of branch instructions in a computer program is predicted by fetching a plurality or group of instructions in a given slot, along with a corresponding prediction. A group global history (gghist) is maintained to indicate of recent program control flow. In addition, a predictor table comprising a plurality of predictions, preferably saturating counters. A particular counter is updated when a branch is encountered. The particular counter is associated with a branch instruction by hashing the fetched instruction group's program counter (PC) with the gghist. To predict multiple branch instruction outcomes, the gghist is hashed with the PC to form an index which is used to access naturally aligned but randomly ordered predictions in the predictor table, which are then reordered based on value of the lower gghits bits. Preferably, instructions are fetched in blocks of eight instructions.

Abstract: A driver circuit provides for selectively changing the state of an output signal, such as a pre-charged dynamic bus signal. The circuit detects whether or not the data is the opposite state as the pre-charged bus signal, and if so, it drives the bus to the appropriate state. The output from the circuit is self-timed when data can be driven onto the bus as soon as data is valid, i.e., data propagates from the input of the circuit to the bus without depending on a clock or other timing edge.