Patents by Inventor Glenn Poole
Glenn Poole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9432212Abstract: A data switching system is disclosed that allows for switching of packets through a plurality of top of rack switches utilizing a logical switching fabric that includes a local TOR switching fabric on a TOR switch and a Core switching fabric on a Core switch. A method of processing packets according to some embodiment can include receiving a packet from a source port into a top of rack switch, the source port being one of a plurality of ports on the top of rack switch, processing a packet header of the packet to determine a destination port; and switching the packet through a logical switching fabric that includes a local switch fabric on the top of rack switch and a Core switching fabric on a Core switch.Type: GrantFiled: August 10, 2012Date of Patent: August 30, 2016Assignee: DELL PRODUCTS L.P.Inventors: Haresh K. Shah, Krishnamurthy Subramanian, Glenn Poole
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Patent number: 9276835Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.Type: GrantFiled: September 1, 2015Date of Patent: March 1, 2016Assignee: Force10 Networks, Inc.Inventors: Glenn Poole, Brad Danofsky, David Haddad, Ann Gui, Heeloo Chung, Joanna Lin
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Publication number: 20150372896Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.Type: ApplicationFiled: September 1, 2015Publication date: December 24, 2015Inventors: Glenn POOLE, Brad DANOFSKY, David HADDAD, Ann GUI, Heeloo CHUNG, Joanna LIN
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Patent number: 9160677Abstract: A network packet is segmented for transfer through a switch fabric. The last segment of the packet is allowed to exceed the maximum size of previous segments so as to increase the switch fabric utilization. Other features are also provided.Type: GrantFiled: July 8, 2014Date of Patent: October 13, 2015Assignee: Force10 Networks, Inc.Inventors: Glenn Poole, Brad Danofsky, David Haddad, Ann Gui, Heeloo Chung, Joanna Lin
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Publication number: 20140321281Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.Type: ApplicationFiled: July 8, 2014Publication date: October 30, 2014Inventors: Glenn POOLE, Brad DANOFSKY, David HADDAD, Ann GUI, Heeloo CHUNG, Joanna LIN
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Patent number: 8804751Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.Type: GrantFiled: October 2, 2006Date of Patent: August 12, 2014Assignee: Force10 Networks, Inc.Inventors: Glenn Poole, Brad Danofsky, David Haddad, Ann Gui, Heeloo Chung, Joanna Lin
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Publication number: 20130044748Abstract: A data switching system is disclosed that allows for switching of packets through a plurality of top of rack switches utilizing a logical switching fabric that includes a local TOR switching fabric on a TOR switch and a Core switching fabric on a Core switch. A method of processing packets according to some embodiment can include receiving a packet from a source port into a top of rack switch, the source port being one of a plurality of ports on the top of rack switch, processing a packet header of the packet to determine a destination port; and switching the packet through a logical switching fabric that includes a local switch fabric on the top of rack switch and a Core switching fabric on a Core switch.Type: ApplicationFiled: August 10, 2012Publication date: February 21, 2013Applicant: DELL PRODUCTS L.P.Inventors: Haresh K. SHAH, Krishnamurthy SUBRAMANIAN, Glenn POOLE
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Patent number: 8218537Abstract: A serial channel switch circuit and modular packet switch using the serial channel switch circuits are disclosed. The serial channel switch circuit has a reconfigurable table for internal logical-to-physical channel switch translation. Depending on the slot in which a card containing such a serial channel switch circuit is inserted in the modular packet switch, its serial channel switch circuit may receive a different set of reconfigurable table values that are specific to that location. A global set of logical channel values can be applied to each card, which performs logical-to-physical channel mapping according to its location in the modular packet switch. Other embodiments are also described and claimed.Type: GrantFiled: May 30, 2008Date of Patent: July 10, 2012Assignee: Force10 Networks, Inc.Inventors: Ann Gui, Krishnamurthy Subramanian, Glenn Poole, Joel R. Goergen, Joanna Lin
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Patent number: 7843830Abstract: Apparatus and methods for epoch retransmission in a packet network device are described. In at least one embodiment, epoch receivers check received epoch data for errors. When an error is detected, a receiver is allowed to request that the entire epoch be retransmitted. All epoch senders retain transmitted epoch data until the time for requesting a retransmission of that data is past. If retransmission is requested by any receiver, the epoch is “replayed.” This approach mitigates the problem of dropping multiple packets (bundled in a large epoch) due to an intraswitch error with the epoch. Other embodiments are also described and claimed.Type: GrantFiled: May 5, 2005Date of Patent: November 30, 2010Assignee: Force 10 Networks, IncInventors: Krishnamurthy Subramanian, Heeloo Chung, Glenn Poole
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Patent number: 6157987Abstract: A method and an apparatus for providing requested data to a pipeline processor. A pipeline processor in a graphics computer system is provided with a data caching mechanism which supplies requested data to one of the stages in the pipeline processor after a request from a prior stage in the pipeline processor. With the sequential nature of the pipeline processor, a prior stage which knows in advance the data which will be requested by a subsequent stage can make a memory request to the disclosed data caching mechanism. When processing reaches the subsequent stage in the pipeline processor, the displayed data caching mechanism provides the requested data to the subsequent processing stage with minimal or no lag time from memory access. In addition, the disclosed data caching mechanism features an adaptive cache memory which is optimized to provide maximum performance based on the particular mode in which the associated pipeline processor is operating.Type: GrantFiled: November 24, 1997Date of Patent: December 5, 2000Assignee: Micron Technology, Inc.Inventors: Subramanian Krishnamurthy, James Peterson, Glenn Poole, Walt Donovan
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Patent number: 5761720Abstract: A method and an apparatus for providing requested data to a pipeline processor. A pipeline processor in a graphics computer system is provided with a data caching mechanism which supplies requested data to one of the stages in the pipeline processor after a request from a prior stage in the pipeline processor. With the sequential nature of the pipeline processor, a prior stage which knows in advance the data which will be requested by a subsequent stage can make a memory request to the data caching mechanism. When processing reaches the subsequent stage in the pipeline processor, the displayed data caching mechanism provides the requested data to the subsequent processing stage with minimal or no lag time from memory access. In addition, the data caching mechanism includes an adaptive cache memory which is optimized to provide maximum performance based on the particular mode in which the associated pipeline processor is operating.Type: GrantFiled: March 15, 1996Date of Patent: June 2, 1998Assignee: Rendition, Inc.Inventors: Subramanian Krishnamurthy, James Peterson, Glenn Poole, Walt Donovan