Abstract: A tester routine is provided that evaluates multiple test pins, on multiple devices under test, at the same time and only if a fail occurs does any evaluation have to be made. In the case of a failing pin on any device only that device with the falling pin is retested until passed or if not passed after a specified time the device is considered a fail.

Abstract: A tester routine is proved that evaluates all test pins, on all devices under test, t the same time and only if a fail does any evaluation have to be made. In the case of a failing pin that device is retested until passed or if not passed after a specified time considered a fail.

Abstract: A method of using a processor-based integrated circuit (IC) tester (12) to automatically invoke diagnostic testing. A diagnostic schedule (30) is user-defined (FIG. 3), and checked by the tester (12) at various times, such as before and after the tester 12 tests an IC lot (FIGS. 6, 7, 8). The schedule (30) has various scheduling parameters that permit diagnostic testing to be scheduled to occur at certain times, at the expiration of intervals, or upon certain events. The schedule (30) also permits different levels of diagnostic testing, each level with its own schedule. The tester (12) is programmed to run an appropriate level of diagnostic testing if more than one level is due to occur.

Abstract: A test system (10) is provided that comprises a controller (14) which controls a test head (12) which comprises a pattern sequence controller (16). An integrated circuit (20) is tested through pin cards (18a) through (18n). A test program (32) operating in controller (14) operates to perform both functional and scanning tests on the integrated circuit (20). Scanning tests are provided for set-up, hold, pulse width, and maximum frequency.