Abstract: A device and method for a peripheral adapter of a dual SCSI bus enclosure is described. An adapter can operate alone or in pairs to provide different modes of operation, including simplex, duplex, and cluster. When used in pairs, two adapters interconnect internally to the enclosure through internal cross-coupling bus repeaters that can be selectively enabled or disabled. The adapters are hot-swappable and have the ability to automatically self configure. In the cluster mode, the adapter supports failover capability from a master adapter to a redundant adapter.

Abstract: A device and method for enclosure processing of a dual SCSI bus enclosure is described. A single SCSI enclosure processor is provided on an adapter that can operate alone or in pairs to provide different modes of operation, including simplex, duplex, and cluster. When used in pairs, two adapters interconnect internally to the enclosure through internal cross-coupling bus repeaters. The adapters have the ability to automatically configure themselves. In the cluster mode, a first enclosure processor on a first adapter assumes an active status, while a second enclosure processor on a second adapter waits in a standby mode. The standby enclosure processor detects when the active enclosure processor has failed, misoperated, or been removed and automatically failsover, assuming the identity of the active enclosure processor, without disruption to the system. Hot-swapping of the adapter boards is therefore possible.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: A system and method for performing view clipping and model clipping of graphics primitives in a geometry accelerator of a computer graphics system. The method includes performing view clipping and model clipping of the graphics primitives in homogeneous window coordinates. The geometry accelerator includes a transform machine, a light machine, a clipping machine, and a plane equation machine. The transform machine receives vertex data defining a graphics primitive, in object coordinates, and transforms the vertex data into homogeneous window coordinates. The light machine receives the transformed vertex data from the transform machine and enhances the transformed vertex data by simulating lighting conditions of the graphics primitive. The light machine provides light enhanced transformed vertex data to the clipping machine.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: An assembler system enables efficient usage of space in a read only memory (ROM) that permits multiway instruction branching. Source code is analyzed and assembled by the assembler system and the assembler system then efficiently places the instructions in the ROM. The source code includes at least the following elements or an equivalent counterpart thereof: next state statements, nonaligned instructions, align statements, and aligned instructions. Next state statements serve as a flag to separate the various instructions. Nonaligned instructions are defined as those instructions that are nonaddressable by other instructions, i.e., those instructions that are not branched to. Align statements serve as a flag to the assembler system that a plurality k (where k is equal to 2.sup.n and where n is a positive integer) of aligned instructions directly follow in succession. Furthermore, aligned instructions are defined as those that are addressable by a plurality of other instructions, i.e.

Abstract: A system and method for performing speculative execution of state machine operation in a graphics accelerator. In accordance with one aspect of the invention, the method includes the step of executing steps in a first state machine that is operating on a graphic primitive. As is known, a graphic primitive is defined by a plurality of vertices. In accordance with the invention, the preferred embodiment receives the coordinate parameters for the second to last primitive vertex. Then it evaluates one or more conditions that indicate whether steps in a second state machine need to be executed, based upon parameters of primitive vertices already received. It then branches to and begins executing steps in another state machine, based upon the tentative conditions, and continuing execution of the steps in the transformation state machine in parallel with the continued execution of the steps in the another state machine.

Abstract: A system and method for reducing an amount of memory that is needed to perform view clipping and model clipping of an input primitive in a geometry accelerator of a computer graphics system. The method includes view clipping the input graphics primitive with each view clipping boundary to determine a view-clipped geometry, storing view-clipped vertex data defining the view clipped geometry in memory, model clipping a view-clipped triangle forming the view-clipped geometry with each user defined model clipping plane to determine a model-clipped geometry, and storing model-clipped vertex data defining the model-clipped geometry in the memory in the memory locations previously occupied by said view-clipped vertex data. The method is repeated until each view-clipped triangle forming the view-clipped geometry has been model-clipped.