Abstract: An improved UART which has a number of channels, with each channel having a set of channel configuration registers. Each channel configuration register includes an interrupt source register. The interrupt source register has a multi-bit interrupt source code which is used to indicate the source of the interrupt. This code is chosen to be compatible with prior UART devices. The device also includes a bus interface, and a plurality of device configuration registers accessible through the bus interface by a user. One of the device configuration registers is an interrupt register which provides a user accessible code to indicate the interrupt source. The code used for the interrupt source is a compressed version of the multiple bit code used in the channel configuration interrupt source register. This compression allows more channels to be represented in a single register, while also conveying the interrupt source information quickly to the user.

Abstract: A UART with a FIFO buffer is provided. A circuit detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS signal for a programmable time delay. The time delay via a register that is programmable by the user. The invention thus provides the programmable delay on the same chip as the UART.

Abstract: A UART with a clock oscillator that has a sleep mode. A counter is connected to the output of the clock oscillator. When the clock oscillator is awakened, the counter counts up to a specified count. Upon reaching the specified count, the output of the counter is enabled, which is connected to an interrupt line for generating an interrupt. In one embodiment, the IC need not be a UART, and no interrupt code (or a default code of all zeros or other default) is provided for the interrupt, thus eliminating the need for an additional interrupt register or additional room in existing interrupt registers. The user, such as a CPU, upon receiving the interrupt will look for an interrupt code. The absence of the interrupt code, combined with the user's knowledge that the integrated circuit was previously asleep, allows the user to determine that the interrupt indicates a clock wake-up.

Abstract: An integrated circuit in which the address and data inputs for a clock register to program a clock is also used for device ID and revision number. A shadow register is provided which is accessible to output the ID and revision number when (1) the regular clock register is addressed, and (2) a particular data input for activating the shadow register appears on the data input to the clock register.

Abstract: A single, standard general purpose register address accesses not only the general purpose register, but, pursuant to user programming, FIFO counter status. In one embodiment, either the receive or transmit FIFO counter status can be accessed. The use of the general purpose register address for this purpose is preferably programmed using a bit from the control register on the chip.

Abstract: A UART compatible to a prior art UART provides a baud rate generator which can accept a higher frequency crystal oscillator to generate baud rates compatible with baud rates generated by the prior art UART without increasing the size of the frequency division circuit. In one embodiment, the UART of the present invention provides the capability for programmable flow control, including flow control for binary file transfers, using user-programmable multiple-character flow control words. In one embodiment, a sleep mode allows power conservation in the UART of the present invention.

Abstract: A unique CVSD CODEC is provided utilizing switched capacitor technology. This CVSD CODEC includes a syllabic filter which provides one of a large number of possible step sizes, thereby allowing the CVSD CODEC to accurately track and convert a wide range of input voltages. The CVSD CODEC includes coincidence logic, which determines how accurately the input voltage is being tracked, and a syllabic filter which provides an appropriate step size based upon the output signals of the coincidence logic. Large step sizes are provided for converting input voltages having large magnitudes, and small step sizes are used to convert input voltages having small magnitudes, thereby providing the very accurate resolution of input voltages over the wide range of magnitudes, while minimizing the bit rate required.

Abstract: An integrator circuit utilizing an operational amplifier (19) and switched capacitor elements (11, 13 and 16) in place of resistors in such a manner as to provide compensation for voltage offsets present in the operational amplifier resulting in an output voltage (V.sub.OUT) free from the effects of voltage offsets inherent in operational amplifiers.