Abstract: Enhanced methods for memory context restore are described. A device may include a physical layer (PHY) having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface, detect values of a plurality of parameters as part of training the interface, and store the detected values as initial training data. The PHY also implements a retraining mode to use the initial training data as seed data to retrain the interface.

Abstract: Enhanced methods for memory context restore are described. A device may include a physical layer (PHY) having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface, detect values of a plurality of parameters as part of training the interface, and store the detected values as initial training data. The PHY also implements a retraining mode to use the initial training data as seed data to retrain the interface.

Abstract: Voltage range for training physical memory is described. A device is configurable to include a PHY having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface over a training voltage range to communicate the command signals or data and an operational mode to use the trained interface to communicate the command signals or data over an operational voltage range that is smaller than the training voltage range.

Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. For each of a number of subsets of the number of memory storage devices, a subset of the number of memory storage devices is selected, each pin of a subset of the number of pins which do not correspond to the subset of the number of memory storage devices is configured with a termination impedance, and the subset of the number of memory storage devices is tested.

Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. For each of a number of subsets of the number of memory storage devices, a subset of the number of memory storage devices is selected, each pin of a subset of the number of pins which do not correspond to the subset of the number of memory storage devices is configured with a termination impedance, and the subset of the number of memory storage devices is tested.

Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. A subset of the number of memory storage devices is selected. A subset of the plurality of pins which do not correspond to the subset of the number of memory storage devices and are not part of a memory map of the computer system is selected. Each pin of the subset of the plurality of pins configured with a termination impedance. The subset of the number of memory storage devices is tested.

Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. For each of a number of subsets of the number of memory storage devices, a subset of the number of memory storage devices is selected, each pin of a subset of the number of pins which do not correspond to the subset of the number of memory storage devices is configured with a termination impedance, and the subset of the number of memory storage devices is tested.

Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.

Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.