Abstract: A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal.

Abstract: The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.