Abstract: Techniques for inferring data to improve the accuracy and completeness of information retrieval are disclosed herein. In some embodiments, a data inference system detects a lack of employment type data for a profile of a user on an online service, with the employment type data identifying at least one type of employment in which the user is interested. In some embodiments, based on the detecting of the lack of employment type data for the profile of the user, the data inference system generates the employment type data based on an inference model and inference data, with the inference data comprising at least one of profile data of the user and a history of the user's interactions with the online service, and the data inference system performs a function of the online service using the generated employment type data.

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Abstract: Techniques for inferring data to improve the accuracy and completeness of information retrieval are disclosed herein. In some embodiments, a data inference system detects a lack of employment type data for a profile of a user on an online service, with the employment type data identifying at least one type of employment in which the user is interested. In some embodiments, based on the detecting of the lack of employment type data for the profile of the user, the data inference system generates the employment type data based on an inference model and inference data, with the inference data comprising at least one of profile data of the user and a history of the user's interactions with the online service, and the data inference system performs a function of the online service using the generated employment type data.

Abstract: The disclosed embodiments provide a system for processing data. During operation, the system obtains an engagement metric correlated with successful usage of a product by a set of customers. Next, the system identifies a threshold for the engagement metric that represents a change in customer growth for the product. The system then uses the threshold and a value of the engagement metric for a customer to characterize a revenue quality of a customer with the product. Finally, the system outputs the revenue quality and the value of the engagement metric for use in managing interaction with the customer.

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.