Patents by Inventor Go Hyun LEE
Go Hyun LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250120079Abstract: A three-dimensional memory device includes first and second isolation patterns extending in a first direction, and adjacent to each other in a second direction intersecting with the first direction; a stack disposed between the first isolation pattern and the second isolation pattern, and including a connection region including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction and an insulating region surrounded by the connection region; and a plurality of stairway-shaped recesses configured in the insulating region and the connecting region, and arranged in the first direction, wherein at least one of the plurality of stairway-shaped recesses comprises a first stairway structure connected to the first isolation pattern, a second stairway structure connected to the second isolation pattern, and a sidewall connecting the first stairway structure and the second stairway structure and disposed in the insulating region.Type: ApplicationFiled: January 11, 2024Publication date: April 10, 2025Inventors: Jin Ho KIM, Sang Hyun SUNG, Go Hyun LEE, Byung Hyun JEON
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Patent number: 12193238Abstract: A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.Type: GrantFiled: November 28, 2022Date of Patent: January 7, 2025Assignee: SK HYNIX INC.Inventors: Go Hyun Lee, Sung Wook Jung
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Publication number: 20240179918Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Go Hyun LEE, Jae Taek KIM, Hye Yeong JUNG
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Patent number: 11930640Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.Type: GrantFiled: February 22, 2021Date of Patent: March 12, 2024Assignee: SK hynix Inc.Inventors: Go Hyun Lee, Jae Taek Kim, Hye Yeong Jung
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Patent number: 11751387Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a peripheral circuit, and a second chip stacked on the first chip that is configured to include a first memory cell array and a second memory cell array. A plurality of transfer circuits are configured to connect a plurality of row lines of the first memory cell array and a plurality of row lines of the second memory cell array to respective global row lines is divided between the first chip and the second chip.Type: GrantFiled: May 19, 2022Date of Patent: September 5, 2023Assignee: SK hynix Inc.Inventor: Go Hyun Lee
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Publication number: 20230093758Abstract: A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Inventors: Go Hyun LEE, Sung Wook JUNG
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Patent number: 11538821Abstract: A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.Type: GrantFiled: August 21, 2020Date of Patent: December 27, 2022Assignee: SK hynix Inc.Inventors: Go Hyun Lee, Sung Wook Jung
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Publication number: 20220278122Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a peripheral circuit, and a second chip stacked on the first chip that is configured to include a first memory cell array and a second memory cell array. A plurality of transfer circuits are configured to connect a plurality of row lines of the first memory cell array and a plurality of row lines of the second memory cell array to respective global row lines is divided between the first chip and the second chip.Type: ApplicationFiled: May 19, 2022Publication date: September 1, 2022Inventor: Go Hyun LEE
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Patent number: 11367732Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a logic circuit, and a second chip stacked on the first chip and configured to include a memory cell array. At least one transfer circuit for connecting a row line of the memory cell array to a global row line is distributed to each of the first chip and the second chip.Type: GrantFiled: July 16, 2020Date of Patent: June 21, 2022Assignee: SK hynix Inc.Inventor: Go Hyun Lee
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Publication number: 20220123008Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.Type: ApplicationFiled: February 22, 2021Publication date: April 21, 2022Inventors: Go Hyun LEE, Jae Taek KIM, Hye Yeong JUNG
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Publication number: 20210242232Abstract: A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.Type: ApplicationFiled: August 21, 2020Publication date: August 5, 2021Inventors: Go Hyun LEE, Sung Wook JUNG
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Publication number: 20210217763Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a logic circuit, and a second chip stacked on the first chip and configured to include a memory cell array. At least one transfer circuit for connecting a row line of the memory cell array to a global row line is distributed to each of the first chip and the second chip.Type: ApplicationFiled: July 16, 2020Publication date: July 15, 2021Inventor: Go Hyun LEE
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Patent number: 10777520Abstract: A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.Type: GrantFiled: September 9, 2019Date of Patent: September 15, 2020Assignee: SK hynix Inc.Inventors: Go-Hyun Lee, Jae-Taek Kim, Jun-Youp Kim, Chang-Man Son
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Patent number: 10566343Abstract: A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: SK hynix Inc.Inventors: Sung-Lae Oh, Jin-Ho Kim, Chang-Man Son, Go-Hyun Lee, Young-Ock Hong
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Publication number: 20200006270Abstract: A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.Type: ApplicationFiled: September 9, 2019Publication date: January 2, 2020Inventors: Go-Hyun LEE, Jae-Taek KIM, Jun-Youp KIM, Chang-Man SON
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Patent number: 10446570Abstract: A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer.Type: GrantFiled: May 24, 2018Date of Patent: October 15, 2019Assignee: SK hynix Inc.Inventors: Go-Hyun Lee, Jae-Taek Kim, Jun-Youp Kim, Chang-Man Son
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Publication number: 20190139976Abstract: A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer.Type: ApplicationFiled: May 24, 2018Publication date: May 9, 2019Inventors: Go-Hyun LEE, Jae-Taek KIM, Jun-Youp KIM, Chang-Man SON
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Publication number: 20180053782Abstract: A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.Type: ApplicationFiled: November 3, 2017Publication date: February 22, 2018Inventors: Sung-Lae OH, Jin-Ho KIM, Chang-Man SON, Go-Hyun LEE, Young-Ock HONG
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Patent number: 9837433Abstract: A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.Type: GrantFiled: September 8, 2016Date of Patent: December 5, 2017Assignee: SK Hynix Inc.Inventors: Sung-Lae Oh, Jin-Ho Kim, Chang-Man Son, Go-Hyun Lee, Young-Ock Hong
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Publication number: 20170323898Abstract: A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.Type: ApplicationFiled: September 8, 2016Publication date: November 9, 2017Inventors: Sung-Lae OH, Jin-Ho KIM, Chang-Man SON, Go-Hyun LEE, Young-Ock HONG