Patents by Inventor Go Hyun LEE

Go Hyun LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120079
    Abstract: A three-dimensional memory device includes first and second isolation patterns extending in a first direction, and adjacent to each other in a second direction intersecting with the first direction; a stack disposed between the first isolation pattern and the second isolation pattern, and including a connection region including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction and an insulating region surrounded by the connection region; and a plurality of stairway-shaped recesses configured in the insulating region and the connecting region, and arranged in the first direction, wherein at least one of the plurality of stairway-shaped recesses comprises a first stairway structure connected to the first isolation pattern, a second stairway structure connected to the second isolation pattern, and a sidewall connecting the first stairway structure and the second stairway structure and disposed in the insulating region.
    Type: Application
    Filed: January 11, 2024
    Publication date: April 10, 2025
    Inventors: Jin Ho KIM, Sang Hyun SUNG, Go Hyun LEE, Byung Hyun JEON
  • Patent number: 12193238
    Abstract: A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: January 7, 2025
    Assignee: SK HYNIX INC.
    Inventors: Go Hyun Lee, Sung Wook Jung
  • Publication number: 20240179918
    Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Go Hyun LEE, Jae Taek KIM, Hye Yeong JUNG
  • Patent number: 11930640
    Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventors: Go Hyun Lee, Jae Taek Kim, Hye Yeong Jung
  • Patent number: 11751387
    Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a peripheral circuit, and a second chip stacked on the first chip that is configured to include a first memory cell array and a second memory cell array. A plurality of transfer circuits are configured to connect a plurality of row lines of the first memory cell array and a plurality of row lines of the second memory cell array to respective global row lines is divided between the first chip and the second chip.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: September 5, 2023
    Assignee: SK hynix Inc.
    Inventor: Go Hyun Lee
  • Publication number: 20230093758
    Abstract: A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 23, 2023
    Inventors: Go Hyun LEE, Sung Wook JUNG
  • Patent number: 11538821
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: December 27, 2022
    Assignee: SK hynix Inc.
    Inventors: Go Hyun Lee, Sung Wook Jung
  • Publication number: 20220278122
    Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a peripheral circuit, and a second chip stacked on the first chip that is configured to include a first memory cell array and a second memory cell array. A plurality of transfer circuits are configured to connect a plurality of row lines of the first memory cell array and a plurality of row lines of the second memory cell array to respective global row lines is divided between the first chip and the second chip.
    Type: Application
    Filed: May 19, 2022
    Publication date: September 1, 2022
    Inventor: Go Hyun LEE
  • Patent number: 11367732
    Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a logic circuit, and a second chip stacked on the first chip and configured to include a memory cell array. At least one transfer circuit for connecting a row line of the memory cell array to a global row line is distributed to each of the first chip and the second chip.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Go Hyun Lee
  • Publication number: 20220123008
    Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.
    Type: Application
    Filed: February 22, 2021
    Publication date: April 21, 2022
    Inventors: Go Hyun LEE, Jae Taek KIM, Hye Yeong JUNG
  • Publication number: 20210242232
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.
    Type: Application
    Filed: August 21, 2020
    Publication date: August 5, 2021
    Inventors: Go Hyun LEE, Sung Wook JUNG
  • Publication number: 20210217763
    Abstract: A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first chip configured to include a logic circuit, and a second chip stacked on the first chip and configured to include a memory cell array. At least one transfer circuit for connecting a row line of the memory cell array to a global row line is distributed to each of the first chip and the second chip.
    Type: Application
    Filed: July 16, 2020
    Publication date: July 15, 2021
    Inventor: Go Hyun LEE
  • Patent number: 10777520
    Abstract: A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Go-Hyun Lee, Jae-Taek Kim, Jun-Youp Kim, Chang-Man Son
  • Patent number: 10566343
    Abstract: A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung-Lae Oh, Jin-Ho Kim, Chang-Man Son, Go-Hyun Lee, Young-Ock Hong
  • Publication number: 20200006270
    Abstract: A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Inventors: Go-Hyun LEE, Jae-Taek KIM, Jun-Youp KIM, Chang-Man SON
  • Patent number: 10446570
    Abstract: A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventors: Go-Hyun Lee, Jae-Taek Kim, Jun-Youp Kim, Chang-Man Son
  • Publication number: 20190139976
    Abstract: A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer.
    Type: Application
    Filed: May 24, 2018
    Publication date: May 9, 2019
    Inventors: Go-Hyun LEE, Jae-Taek KIM, Jun-Youp KIM, Chang-Man SON
  • Publication number: 20180053782
    Abstract: A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.
    Type: Application
    Filed: November 3, 2017
    Publication date: February 22, 2018
    Inventors: Sung-Lae OH, Jin-Ho KIM, Chang-Man SON, Go-Hyun LEE, Young-Ock HONG
  • Patent number: 9837433
    Abstract: A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: December 5, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sung-Lae Oh, Jin-Ho Kim, Chang-Man Son, Go-Hyun Lee, Young-Ock Hong
  • Publication number: 20170323898
    Abstract: A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.
    Type: Application
    Filed: September 8, 2016
    Publication date: November 9, 2017
    Inventors: Sung-Lae OH, Jin-Ho KIM, Chang-Man SON, Go-Hyun LEE, Young-Ock HONG