Patents by Inventor Go Iwasaki

Go Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Output buffer circuit and semiconductor memory using the same
    Patent number: 7280411
    Abstract: An output buffer circuit of the present invention includes a plurality of unit circuits in each of which a pull-up transistor controlled by a first input signal is connected between a high-potential power supply and common node, and a pull-down transistor controlled by a second input signal is connected between the common node and a low-potential power supply, an output terminal connected to a common connecting point of the common nodes of the plurality of unit circuits, and first resistors formed respectively between the common nodes of the plurality of unit circuits and the common connecting point.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: October 9, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Go Iwasaki
  • Output buffer circuit and semiconductor memory using the same
    Publication number: 20040136221
    Abstract: An output buffer circuit of the present invention includes a plurality of unit circuits in each of which a pull-up transistor controlled by a first input signal is connected between a high-potential power supply and common node, and a pull-down transistor controlled by a second input signal is connected between the common node and a low-potential power supply, an output terminal connected to a common connecting point of the common nodes of the plurality of unit circuits, and first resistors formed respectively between the common nodes of the plurality of unit circuits and the common connecting point.
    Type: Application
    Filed: November 25, 2003
    Publication date: July 15, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Go Iwasaki
  • Output buffer circuit and semiconductor memory using the same
    Patent number: RE41838
    Abstract: An output buffer circuit of the present invention includes a plurality of unit circuits in each of which a pull-up transistor controlled by a first input signal is connected between a high-potential power supply and common node, and a pull-down transistor controlled by a second input signal is connected between the common node and a low-potential power supply, an output terminal connected to a common connecting point of the common nodes of the plurality of unit circuits, and first resistors formed respectively between the common nodes of the plurality of unit circuits and the common connecting point.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: October 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Go Iwasaki