Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a pillar, a strip part, a plurality of first contacts, and a second contact. The stacked body includes a plurality of conductive layers stacked via an insulating layer, and includes, at each of opposite ends in a first direction, a first staircase part in which the conductive layers are terminated stepwise. The pillar extends in the stacked body in a stacking direction of the stacked body, and form memory cells at positions intersecting with at least some conductive layers of the plurality of conductive layers. The strip part divides the stacked body in the first direction by extending in a second direction crossing the first direction. The plurality of first contacts are arranged in the first staircase part, in which each of the first contacts is connected to one of the conductive layers at each step of the first staircase part.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

Abstract: A semiconductor storage device according to an embodiment includes a stacked body in which a conductive layer and an insulating layer are stacked alternately in a first direction, a plurality of columnar bodies that extend in the first direction inside the stacked body and each include a semiconductor body, a plurality of charge storage films that are disposed between at least one of a plurality of the conductive layers and each of a plurality of the semiconductor bodies, a plurality of bit lines that extend above the stacked body in a second direction intersecting the first direction, an interlayer insulating layer that is between the stacked body and the bit lines, and contacts each of which penetrates the interlayer insulating layer and is electrically connected to one of the plurality of bit lines, in which the contacts have a first contact that is connected to one of the columnar bodies and a second contact that is connected to a plurality of the columnar bodies.

Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

Abstract: A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.

Abstract: A semiconductor device of an embodiment includes first and second structures arranged in a first hierarchy, in which the first and second structures are repeatedly arranged in a first direction along a plane of the first hierarchy, and a distance between geometric centers of the first and second structures in a minimum unit of repetition of the first and second structures differs between a first position and a second position in the first direction.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.

Abstract: A semiconductor device includes a first substrate, a first insulating film disposed on the first substrate, and a semiconductor layer disposed on the first insulating film. The semiconductor device further includes a metal layer with a first portion and a second portion. The first portion is disposed on the semiconductor layer, and the second portion includes a bonding pad and is disposed on the first insulating film without the semiconductor layer interposed between the second portion and the first insulating film.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.

Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

Abstract: A semiconductor memory device includes a substrate, a first stack, a plurality of first columnar portions, a second stack, a plurality of second columnar portions, and a third stack. In the first stack, first conductive layers and first insulating layers are alternately stacked in a thickness direction of the substrate. Each of the plurality of first pillars extends inside the first stack in the thickness direction. In the second stack, second conductive layers and second insulating layers are alternately stacked in the thickness direction. Each of the plurality of second pillars extends inside the second stack in the thickness direction. The third stack is positioned between the first stack and the second stack in the first direction. In the third stack, third insulating layers and fourth insulating layers including a material different from a material of the third insulating layer are alternately stacked in the thickness direction of the substrate.

Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

Abstract: A semiconductor device of an embodiment includes first and second structures arranged in a first hierarchy, in which the first and second structures are repeatedly arranged in a first direction along a plane of the first hierarchy, and a distance between geometric centers of the first and second structures in a minimum unit of repetition of the first and second structures differs between a first position and a second position in the first direction.

Abstract: A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.

Abstract: A semiconductor light emitting device according to an embodiment includes a stacked body. The stacked body includes a first semiconductor layer of a first conductivity type, a light emitting layer is provided on the first semiconductor layer, and a second semiconductor layer of a second conductivity type provided on the light emitting layer. The stacked body includes a first protrusion on an upper surface of the stacked body. The first protrusion protrudes in a first direction from the first semiconductor layer to the light emitting layer. Length of the first protrusion in a second direction perpendicular to the first direction decreases toward the first direction. The first protrusion includes a first portion and a second portion. The first portion has a first side surface inclined with respect to the first direction. The second portion is provided below the first portion and having a second side surface inclined with respect to the first direction.

Abstract: A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.