Patents by Inventor Go SHIKATA
Go SHIKATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230326532Abstract: A memory device having a memory array with a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines and control logic coupled with the memory array. The control logic perform operations including: determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of the plurality of memory cells, wherein the metadata value comprises at least one of a failed byte count or a failed bit count; adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution.Type: ApplicationFiled: March 3, 2023Publication date: October 12, 2023Inventors: Go Shikata, Kitae Park
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Patent number: 11664076Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory block including first word lines for respective first memory cells of the first memory block; a second memory block including second word lines for respective second memory cells of the second memory block; first diffusion regions coupled to the first word lines; second diffusion regions adjacent the first diffusion regions, the second diffusion regions coupled to the second word lines; and a circuit to apply a voltage to the second diffusion regions in a write operation performed on the first memory block.Type: GrantFiled: March 30, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventors: Go Shikata, Shigekazu Yamada
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Patent number: 11574663Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.Type: GrantFiled: December 2, 2020Date of Patent: February 7, 2023Assignee: Kioxia CorporationInventors: Keisuke Nakatsuka, Tomoya Sanuki, Takashi Maeda, Go Shikata, Hideaki Aochi
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Publication number: 20220208274Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory block including first control gates for respective first memory cells of the first memory block; a second memory block including second control gates for respective second memory cells of the second memory block; first diffusion regions coupled to the first control gates; second diffusion regions adjacent the first diffusion regions, the second diffusion regions coupled to the second control gates; and a circuit to apply a voltage to the second diffusion regions in a write operation performed on the first memory block.Type: ApplicationFiled: March 30, 2021Publication date: June 30, 2022Applicant: Micron Technology, Inc.Inventors: Go Shikata, Shigekazu Yamada
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Patent number: 11250915Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.Type: GrantFiled: October 12, 2020Date of Patent: February 15, 2022Assignee: Toshiba Memory CorporationInventors: Hiroshi Maejima, Katsuaki Isobe, Naohito Morozumi, Go Shikata, Susumu Fujimura
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Patent number: 11164888Abstract: A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.Type: GrantFiled: September 24, 2020Date of Patent: November 2, 2021Assignee: KIOXIA CORPORATIONInventors: Takuya Futatsuyama, Go Shikata
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Publication number: 20210090616Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.Type: ApplicationFiled: December 2, 2020Publication date: March 25, 2021Applicant: Toshiba Memory CorporationInventors: Keisuke NAKATSUKA, Tomoya SANUKI, Takashi MAEDA, Go SHIKATA, Hideaki AOCHI
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Publication number: 20210027843Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.Type: ApplicationFiled: October 12, 2020Publication date: January 28, 2021Applicant: Toshiba Memory CorporationInventors: Hiroshi MAEJIMA, Katsuaki ISOBE, Naohito MOROZUMI, Go SHIKATA, Susumu FUJIMURA
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Publication number: 20210013227Abstract: A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.Type: ApplicationFiled: September 24, 2020Publication date: January 14, 2021Inventors: Takuya Futatsuyama, Go Shikata
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Patent number: 10867641Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.Type: GrantFiled: March 18, 2019Date of Patent: December 15, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Keisuke Nakatsuka, Tomoya Sanuki, Takashi Maeda, Go Shikata, Hideaki Aochi
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Patent number: 10839913Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.Type: GrantFiled: September 11, 2019Date of Patent: November 17, 2020Assignee: Toshiba Memory CorporationInventors: Hiroshi Maejima, Katsuaki Isobe, Naohito Morozumi, Go Shikata, Susumu Fujimura
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Patent number: 10825829Abstract: A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.Type: GrantFiled: March 18, 2019Date of Patent: November 3, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takuya Futatsuyama, Go Shikata
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Patent number: 10783975Abstract: A semiconductor memory device includes first and second memory transistors and first and second word lines connected to gate electrodes of the memory transistors. The semiconductor memory device is configured such that a first write operation to the first memory transistor, a second write operation to the second memory transistor, a third write operation to the first memory transistor, and a fourth write operation to the second memory transistor are executed in this order. In the first and second write operations, data write is performed using only a program operation. In the third and fourth write operations, data write is performed using the program operation and the verify operation.Type: GrantFiled: September 5, 2019Date of Patent: September 22, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shimura, Koki Ueno, Go Shikata
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Publication number: 20200273530Abstract: A semiconductor memory device includes first and second memory transistors and first and second word lines connected to gate electrodes of the memory transistors. The semiconductor memory device is configured such that a first write operation to the first memory transistor, a second write operation to the second memory transistor, a third write operation to the first memory transistor, and a fourth write operation to the second memory transistor are executed in this order. In the first and second write operations, data write is performed using only a program operation. In the third and fourth write operations, data write is performed using the program operation and the verify operation.Type: ApplicationFiled: September 5, 2019Publication date: August 27, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shimura, Koki Ueno, Go Shikata
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Publication number: 20200176061Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.Type: ApplicationFiled: September 11, 2019Publication date: June 4, 2020Applicant: Toshiba Memory CorporationInventors: Hiroshi MAEJIMA, Katsuaki ISOBE, Naohito MOROZUMO, Go SHIKATA, Susumu FUJIMURA
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Publication number: 20200090710Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.Type: ApplicationFiled: March 18, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Keisuke NAKATSUKA, Tomoya SANUKI, Takashi MAEDA, Go SHIKATA, Hideaki AOCHI
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Patent number: 10529731Abstract: A semiconductor memory device includes a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor that are connected in series. A word line is coupled to a gate of the third memory cell transistor. A controller is configured to set a first upper limit value for voltages applied to the word line during writing of data to the first memory cell transistor and a second upper limit value for voltages applied to the word line during writing of data to the second memory cell transistor. The second upper limit value is different from the first upper limit value.Type: GrantFiled: March 1, 2018Date of Patent: January 7, 2020Assignee: Toshiba Memory CorporationInventors: Go Shikata, Yasuhiro Shimura
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Publication number: 20190214406Abstract: A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.Type: ApplicationFiled: March 18, 2019Publication date: July 11, 2019Inventors: Takuya Futatsuyama, Go Shikata
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Patent number: 10332593Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively. The word line is electrically connected to the first and second memory cells. The first and second bit lines are electrically connected to the first and second memory cells, respectively. The driver increases gradually the voltage of the word line. When the voltage of the word line is increased gradually by the driver, the sense amplifier senses the first and second threshold voltages in ascending order.Type: GrantFiled: December 16, 2016Date of Patent: June 25, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takahiko Sasaki, Go Shikata, Tomonori Kurosawa, Rieko Funatsuki
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Patent number: 10269828Abstract: A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.Type: GrantFiled: March 1, 2018Date of Patent: April 23, 2019Assignee: Toshiba Memory CorporationInventors: Takuya Futatsuyama, Go Shikata