Patents by Inventor Godefridus Adrianus Maria Hurkx
Godefridus Adrianus Maria Hurkx has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10403747Abstract: A semiconductor device and a method of making the same is disclosed. The device includes a substrate having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of contacts. At least one of the contacts includes an ohmic contact portion located on a major surface of the substrate. The ohmic contact portion comprises a first electrically conductive material. The at least one of the contacts also includes a trench extending down into the substrate from the major surface. The trench passes through the AlGaN layer and into the GaN layer. The trench is at least partially filled with a second electrically conductive material. The second electrically conductive material is a different electrically conductive material to the first electrically conductive material.Type: GrantFiled: November 18, 2016Date of Patent: September 3, 2019Assignee: Nexperia B.V.Inventors: Godefridus Adrianus Maria Hurkx, Johannes Josephus Theodorus Marinus Donkers, Jan Sonsky, Jeroen Antoon Croon
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Patent number: 10157809Abstract: A semiconductor device and a method of making the same are disclosed. The device includes a substrate including an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of electrical contacts located on a major surface of the substrate. The device further includes a plurality of passivation layers located on the major surface of the substrate. The plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface. The first and second passivation materials are different passivation materials. The different passivation materials may be compositions of silicon nitride that include different proportions of silicon.Type: GrantFiled: November 18, 2016Date of Patent: December 18, 2018Assignee: Nexperia BVInventors: Johannes Josephus Theodorus Marinus Donkers, Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Mark Andrzej Gajda, Jan Sonsky
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Patent number: 9929263Abstract: A semiconductor device and a method of making the same. The device includes a substrate having an AlGaN layer located on one or more GaN layers, for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a source contact. The device further includes a drain contact. The device also includes a gate contact located between the source contact and the drain contact. The gate contact includes a gate electrode. The gate contact also includes an electrically insulating layer located between the gate electrode and the AlGaN layer. The insulating layer includes at least one aperture for allowing holes generated during an off-state of the device to exit the device through the gate electrode.Type: GrantFiled: December 9, 2016Date of Patent: March 27, 2018Assignee: Nexperia B.V.Inventors: Jan Sonsky, Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers
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Publication number: 20170194473Abstract: A semiconductor device and a method of making the same. The device includes a substrate having an AlGaN layer located on one or more GaN layers, for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a source contact. The device further includes a drain contact. The device also includes a gate contact located between the source contact and the drain contact. The gate contact includes a gate electrode. The gate contact also includes an electrically insulating layer located between the gate electrode and the AlGaN layer. The insulating layer includes at least one aperture for allowing holes generated during an off-state of the device to exit the device through the gate electrode.Type: ApplicationFiled: December 9, 2016Publication date: July 6, 2017Inventors: Jan Sonsky, Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers
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Publication number: 20170170089Abstract: A semiconductor device and a method of making the same are disclosed. The device includes a substrate including an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of electrical contacts located on a major surface of the substrate. The device further includes a plurality of passivation layers located on the major surface of the substrate. The plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface. The first and second passivation materials are different passivation materials.Type: ApplicationFiled: November 18, 2016Publication date: June 15, 2017Inventors: Johannes Josephus Theodorus Marinus Donkers, Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Mark Andrzej Gajda, Jan Sonsky
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Publication number: 20170154988Abstract: A semiconductor device and a method of making the same is disclosed. The device includes a substrate having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of contacts. At least one of the contacts includes an ohmic contact portion located on a major surface of the substrate. The ohmic contact portion comprises a first electrically conductive material. The at least one of the contacts also includes a trench extending down into the substrate from the major surface. The trench passes through the AlGaN layer and into the GaN layer. The trench is at least partially filled with a second electrically conductive material. The second electrically conductive material is a different electrically conductive material to the first electrically conductive material.Type: ApplicationFiled: November 18, 2016Publication date: June 1, 2017Inventors: Godefridus Adrianus Maria Hurkx, Johannes Josephus Theodorus Marinus Donkers, Jan Sonsky, Jeroen Antoon Croon
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Patent number: 9391187Abstract: In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them.Type: GrantFiled: May 27, 2015Date of Patent: July 12, 2016Assignee: NXP B.V.Inventors: Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers, Stephan Bastiaan Simon Heil, Jan Sonsky
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Patent number: 9385226Abstract: A heterojunction semiconductor device (200) comprising a substrate (202) and a multilayer structure disposed on the substrate. The multilayer structure comprising a first layer (204), which comprises a first semiconductor disposed on top of the substrate, and a second layer (206), which comprises a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas (220) forms adjacent to the interface. The multilayer structure also comprising a passivation layer, which comprises a semiconductor passivation layer (208) disposed on top of the second layer. The heterojunction semiconductor device also includes a first terminal (210) electrically coupled to a first area of the heterojunction semiconductor device; and a second terminal (212) electrically coupled to a second area of the heterojunction semiconductor device.Type: GrantFiled: February 3, 2015Date of Patent: July 5, 2016Assignee: NXP B.V.Inventors: Johannes Josephus Theodorus Marinus Donkers, Godefridus Adrianus Maria Hurkx, Stephan Bastiaan Simon Heil, Michael Antoine Armand in 't Zandt
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Patent number: 9349819Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.Type: GrantFiled: May 18, 2015Date of Patent: May 24, 2016Assignee: NXP B.V.Inventors: Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers, Jan Sonsky, Stephen John Sque, Andreas Bernardus Maria Jansman, Markus Mueller, Stephan Heil, Tim Boettcher
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Publication number: 20160020296Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.Type: ApplicationFiled: May 18, 2015Publication date: January 21, 2016Inventors: Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers, Jan Sonsky, Stephen John Sque, Andreas Bernardus Maria Jansman, Markus Mueller, Stephan Heil, Tim Boettcher
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Publication number: 20150357456Abstract: In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them.Type: ApplicationFiled: May 27, 2015Publication date: December 10, 2015Inventors: Godefridus Adrianus Maria HURKX, Jeroen Antoon CROON, Johannes Josephus Theodorus Marinus DONKERS, Stephan Bastiaan Simon HEIL, Jan SONSKY
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Patent number: 9142763Abstract: An electronic component (100), a first electrode (101), a second electrode (102), and a convertible structure (103) electrically coupled between the first electrode (101) and the second electrode (102), being convertible between at least two states by heating and having different electrical properties in different ones of the at least two states, wherein the convertible structure (103) comprises terminal portions (104, 105) connected to the first electrode (101) and to the second electrode (102), respectively, and comprises a line portion (106) between the terminal portions (104, 105), the line portion (106) having a smaller width or thickness than the terminal portions (104, 105), and wherein the convertible structure (103) is arranged with respect to the first electrode (101) and the second electrode (102) so that, in one of the at least two states, the line portion (106) has an amorphous ‘Spot (107) extending along only a part of the line portion (106).Type: GrantFiled: June 18, 2008Date of Patent: September 22, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Godefridus Adrianus Maria Hurkx
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Publication number: 20150228774Abstract: A heterojunction semiconductor device (200) comprising a substrate (202) and a multilayer structure disposed on the substrate. The multilayer structure comprising a first layer (204), which comprises a first semiconductor disposed on top of the substrate, and a second layer (206), which comprises a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas (220) forms adjacent to the interface. The multilayer structure also comprising a passivation layer, which comprises a semiconductor passivation layer (208) disposed on top of the second layer. The heterojunction semiconductor device also includes a first terminal (210) electrically coupled to a first area of the heterojunction semiconductor device; and a second terminal (212) electrically coupled to a second area of the heterojunction semiconductor device.Type: ApplicationFiled: February 3, 2015Publication date: August 13, 2015Inventors: Johannes Josephus Theodorus Marinus Donkers, Godefridus Adrianus Maria Hurkx, Stephan Bastiaan Simon Heil, Michael Antoine Armand In 't Zandt
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Patent number: 8962461Abstract: Consistent with an example embodiment, a GaN heterojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectriclayer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.Type: GrantFiled: December 16, 2013Date of Patent: February 24, 2015Assignee: NXP B.V.Inventors: Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers, Stephan Heil, Jan Sonsky
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Patent number: 8885399Abstract: A phase change memory (PCM) architecture and a method for writing a PCM architecture are described. In one embodiment, a PCM architecture includes a PCM array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. The bit line driver circuits are connected to the PCM array and the electrical ground. Other embodiments are also described.Type: GrantFiled: March 29, 2011Date of Patent: November 11, 2014Assignee: NXP B.V.Inventors: Maurits Mario Nicolaas Storms, Erik Maria van Bussel, Godefridus Adrianus Maria Hurkx, Michiel Jos van Duuren
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Publication number: 20140167064Abstract: A GaN hetereojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectric layer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.Type: ApplicationFiled: December 16, 2013Publication date: June 19, 2014Applicant: NXP B.V.Inventors: Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers, Stephan Heil, Jan Sonsky
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Publication number: 20130320400Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.Type: ApplicationFiled: May 15, 2013Publication date: December 5, 2013Applicant: NXP B.V.Inventors: Godefridus Adrianus Maria HURKX, Jeroen Antoon CROON, Johannes Josephus Theodorus Marinus Donkers, Jan Sonsky, Stephen John SQUE, Andreas Bernardus Maria JANSMAN, Markus MUELLER, Stephan HEIL, Tim BOETTCHER
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Publication number: 20120250401Abstract: A phase change memory (PCM) architecture and a method for writing a PCM architecture are described. In one embodiment, a PCM architecture includes a PCM array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. The bit line driver circuits are connected to the PCM array and the electrical ground. Other embodiments are also described.Type: ApplicationFiled: March 29, 2011Publication date: October 4, 2012Applicant: NXP B.V.Inventors: Maurits Mario Nicolaas Storms, Erik Maria van Bussel, Godefridus Adrianus Maria Hurkx, Michiel Jos van Duuren
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Patent number: 8114774Abstract: The invention relates to a method of manufacturing a semiconductor device with a substrate and a semiconductor body, whereby in the semiconductor body a semiconductor element is formed by means of a mesa-shaped protrusion of the semiconductor body, which is formed on the surface of the semiconductor device as a nano wire, whereupon a layer of a material is deposited over the semiconductor body and the resulting structure is subsequently planarized in a chemical-mechanical polishing process such that an upper side of the nano wire becomes exposed. According to the invention, a further layer of a further material is deposited over the semiconductor body with the nano wire before the layer of the material is deposited, which further layer is given a thickness smaller than the height of the nano wire, and a material is chosen for the further material such that, viewed in projection, the transition between the layer and the further layer is discernible before the nano wire is reached.Type: GrantFiled: June 6, 2007Date of Patent: February 14, 2012Assignee: NXP B.V.Inventors: Godefridus Adrianus Maria Hurkx, Johannes Josephus Theodorus Marinus Donkers
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Patent number: 7915709Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.Type: GrantFiled: July 7, 2005Date of Patent: March 29, 2011Assignee: NXP B.V.Inventors: Godefridus Adrianus Maria Hurkx, Prabhat Agarwal, Abraham Rudolf Balkenende, Petrus Hubertus Cornelis Magnee, Melanie Maria Hubertina Wagemans, Erik Petrus Antonius Maria Bakkers, Erwin Hijzen