Patents by Inventor Godfrey Da Costa
Godfrey Da Costa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11900109Abstract: The present invention relates to an execution unit for executing a computer program comprising a sequence of instructions, which include a masking instruction. The execution unit is configured to execute the masking instruction which, when executed by the execution unit, masks randomly selected values from a source operand of n values and retains other original values from the source operand to generate a result which includes original values from the source operand and symbols in place of the selected values.Type: GrantFiled: February 1, 2018Date of Patent: February 13, 2024Assignee: GRAPHCORE LIMITEDInventors: Stephen Felix, Simon Christian Knowles, Godfrey Da Costa
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Patent number: 11762641Abstract: A method of allocating variables to computer memory includes determining at compile time when each of the plurality of variables is live in a memory region and allocating a memory region to each variable wherein at least some variables are allocated at compile time to overlapping memory regions to be stored in those memory regions at runtime at non-overlapping times.Type: GrantFiled: December 3, 2020Date of Patent: September 19, 2023Assignee: Graphcore LimitedInventors: Godfrey Da Costa, Timothy David Hutt
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Publication number: 20230281013Abstract: A processing device comprising a plurality of operand registers, wherein a first subset of the operand registers are configured to store state information for a plurality of bins, comprising a range of values and a bin count associated with each respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for each of the floating-point values: identify based on an exponent of the respective floating-point value, each one of the plurality of bins for which the respective floating-point value falls within the associated range of values; and increment the bin count associated with the identified bins.Type: ApplicationFiled: February 28, 2023Publication date: September 7, 2023Inventors: Alan ALEXANDER, Simon KNOWLES, Godfrey Da Costa, Badreddine NOUNE
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Publication number: 20230281015Abstract: A processing device comprising: a control register configured to store a scaling factor; at least one execution unit configured to execute instructions to perform arithmetic operations on input floating-point numbers provided according to a first floating-point format, wherein each of the input floating-point numbers provided according to the first floating-point format comprises a predetermined number of bits, wherein the at least one execution unit is configured to, in response to execution of an instance of a first of the instructions: perform processing of a first set of the input floating-point numbers to generate a result value, the result value provided in a further format and comprising more the predetermined number of bits, enabling representation of a greater range of values than is representable in the first floating-point format; and apply the scaling factor specified in the control register to increase or decrease an exponent of the result value.Type: ApplicationFiled: February 27, 2023Publication date: September 7, 2023Inventors: Alan ALEXANDER, Simon KNOWLES, Stephen FELIX, Carlo LUSCHI, Badreddine NOUNE, Mrudula GORE, Godfrey DA COSTA, Edward ANDREWS, Dominic MASTERS
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Patent number: 11720332Abstract: A method for generating an executable program to run on one or more processor modules. The method comprises: receiving a graph comprising a plurality of data nodes, compute vertices and edges; and compiling the graph into an executable program including one or more types of multi-access instruction each of which performs at least two memory access (load and/or store) operations in a single instruction. The memory on each processor module comprises multiple memory banks whereby the same bank cannot be accessed by different load or store operations in the same instruction. The compilation comprises assigning instances of the multi-access instructions to implement at least some of the graph edges, and allocating the data to memory addresses within different ones of the banks. The allocating is performed subject to one or more constraints, including at least that different load/store operations should not access the same memory bank in the same instruction.Type: GrantFiled: July 31, 2019Date of Patent: August 8, 2023Assignee: GRAPHCORE LIMITEDInventors: David Lacey, Godfrey Da Costa
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Publication number: 20230214255Abstract: A processing device comprising: at least one execution unit configured to interleave execution of a plurality of worker threads, wherein each of the worker threads is configured to execute a same set of code to perform operations on a different set of data held in an input buffer of a memory of the processing device and output the results data to an output buffer. An instruction is executed so as to cause a plurality of operand registers, each of which is associated with one of the worker threads, to be populated with one or more variables enabling each worker to determine where in the input buffer is located its set of input data and where to store its results data.Type: ApplicationFiled: October 28, 2022Publication date: July 6, 2023Inventors: Alan ALEXANDER, Stephen FELIX, Edward ANDREWS, Godfrey DA COSTA
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Publication number: 20230185880Abstract: A computer-implemented method comprising: processing data in a neural network to compute a network tensor comprising a plurality of tensor elements represented in an initial numerical format; computing a histogram of tensor elements; selecting a target numerical format, the target numerical format having a lower precision than the initial numerical format; evaluating a metric based on the histogram of tensor elements and the target numerical format, the metric indicating a degree of accuracy of a representation of the network tensor in the target numerical format; and based on the evaluated metric, converting the plurality of tensor elements from the initial numerical format to the target numerical format.Type: ApplicationFiled: December 15, 2022Publication date: June 15, 2023Inventors: Godfrey Da Costa, Badreddine Noune, Daniel Justus, Carlo Luschi
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Publication number: 20230186095Abstract: A computer-implemented method of training a multi-layer neural network comprising a set of network weights, comprising: processing the training data in respective forward and backward passes through multiple layers, the forward pass comprising computing a set of activations in dependence on the network weights and training data, and the backward pass comprising: computing gradients of a pre-determined loss function with respect to the network weights and/or activations, wherein an adjustment parameter is applied to at least a subset of values in the neural network, the values comprising at least one of: the network weights, the activations, the gradients with respect to activations and the gradients with respect to weights; updating the network weights in dependence on the computed gradients; computing a proportion of the subset of values falling above a predefined threshold; and updating the adjustment parameter in dependence on the computed proportion.Type: ApplicationFiled: December 15, 2022Publication date: June 15, 2023Inventors: Godfrey Da Costa, Badreddine Noune, Daniel Justus, Carlo Luschi
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Patent number: 11334320Abstract: An execution unit configured to execute a computer program instruction to generate random numbers based on a predetermined probability distribution. The execution unit comprises a hardware pseudorandom number generator configured to generate at least randomised bit string on execution of the instruction and adding circuitry which is configured to receive a number of bit sequences of a predetermined bit length selected from the randomised bit string and to sum them to produce a result.Type: GrantFiled: February 21, 2020Date of Patent: May 17, 2022Assignee: GRAPHCORE LIMITEDInventors: Stephen Felix, Godfrey Da Costa
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Publication number: 20220138564Abstract: A method of processing batches of data in a computer comprising a plurality of pipelined stages each providing one or more layers of a machine learning model. The method comprises: processing a first batch of data in the pipeline processing stages, each layer of the model using an activation function and weights for that layer to generate an output activation, wherein an output layer generates an output of the model. The method further comprises, for each layer: computing an estimated gradient of a loss function; generating updated weights by processing the estimated gradient with respect to the weights for the first batch using a learning rate for the model; and storing the updated weights for processing on the next batch of data. Updated weights are generated using a modulation factor based on the number of processing stages between that layer and the output layer.Type: ApplicationFiled: June 30, 2021Publication date: May 5, 2022Inventors: Godfrey DA COSTA, Carlo LUSCHI
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Publication number: 20220051095Abstract: A computer comprising a plurality of processing units, each processing unit having an execution unit and access to computer memory which stores code executable by the execution unit and input values of an input vector to be processed by the code, the code, when executed, configured to access the computer memory to obtain multiple pairs of input values of the input vector, determine a maximum or corrected maximum input value of each pair as a maximum result element, determine and store in a computer memory a maximum or corrected maximum result of each pair of maximum result elements as an approximation to the natural log of the sum of the exponents of the input values and access the computer memory to obtain each input value and apply it to the maximum or corrected maximum result to generate each output value of a Softmax output vector.Type: ApplicationFiled: June 1, 2021Publication date: February 17, 2022Inventors: Carlo LUSCHI, Godfrey DA COSTA, Badreddine NOUNE
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Publication number: 20220019531Abstract: A method of allocating variables to computer memory includes determining at compile time when each of the plurality of variables is live in a memory region and allocating a memory region to each variable wherein at least some variables are allocated at compile time to overlapping memory regions to be stored in those memory regions at runtime at non-overlapping times.Type: ApplicationFiled: December 3, 2020Publication date: January 20, 2022Inventors: Godfrey DA COSTA, Timothy David HUTT
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Publication number: 20200319861Abstract: A method for generating an executable program to run on one or more processor modules. The method comprises: receiving a graph comprising a plurality of data nodes, compute vertices and edges; and compiling the graph into an executable program including one or more types of multi-access instruction each of which performs at least two memory access (load and/or store) operations in a single instruction. The memory on each processor module comprises multiple memory banks whereby the same bank cannot be accessed by different load or store operations in the same instruction. The compilation comprises assigning instances of the multi-access instructions to implement at least some of the graph edges, and allocating the data to memory addresses within different ones of the banks. The allocating is performed subject to one or more constraints, including at least that different load/store operations should not access the same memory bank in the same instruction.Type: ApplicationFiled: July 31, 2019Publication date: October 8, 2020Inventors: David Lacey, Godfrey Da Costa
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Publication number: 20200192636Abstract: The present relates to invention deals with an execution unit configured to execute a computer program instruction to generate random numbers based on a predetermined probability distribution. The execution unit comprises a hardware pseudorandom number generator configured to generate at least randomised bit string on execution of the instruction and adding circuitry which is configured to receive a number of bit sequences of a predetermined bit length selected from the randomised bit string and to sum them to produce a result.Type: ApplicationFiled: February 21, 2020Publication date: June 18, 2020Inventors: Stephen Felix, Godfrey Da Costa
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Patent number: 10613833Abstract: The present relates to invention deals with an execution unit configured to execute a computer program instruction to generate random numbers based on a predetermined probability distribution. The execution unit comprises a hardware pseudorandom number generator configured to generate at least randomised bit string on execution of the instruction and adding circuitry which is configured to receive a number of bit sequences of a predetermined bit length selected from the randomised bit string and to sum them to produce a result.Type: GrantFiled: February 1, 2018Date of Patent: April 7, 2020Assignee: Graphcore LimitedInventors: Stephen Felix, Godfrey Da Costa
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Publication number: 20190121639Abstract: The present invention relates to an execution unit for executing a computer program comprising a sequence of instructions, which include a masking instruction. The execution unit is configured to execute the masking instruction which when executed by the execution unit masks randomly selected values from a source operand of n values and retains other original values from the source operand to generate a result which includes original values from the source operand and the masked values in their respective original locations.Type: ApplicationFiled: February 1, 2018Publication date: April 25, 2019Applicant: Graphcore LimitedInventors: Stephen Felix, Simon Christian Knowles, Godfrey Da Costa
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Publication number: 20190121616Abstract: The present relates to invention deals with an execution unit configured to execute a computer program instruction to generate random numbers based on a predetermined probability distribution. The execution unit comprises a hardware pseudorandom number generator configured to generate at least randomised bit string on execution of the instruction and adding circuitry which is configured to receive a number of bit sequences of a predetermined bit length selected from the randomised bit string and to sum them to produce a result.Type: ApplicationFiled: February 1, 2018Publication date: April 25, 2019Applicant: Graphcore LimitedInventors: Stephen Felix, Godfrey Da Costa
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Publication number: 20100304769Abstract: An inter-radio-access-technology device comprising: an interface for communicating over a wireless cellular network, and a processor arranged to execute code for performing operations handling communications via the interface according to a plurality of different radio access technologies. The processor is operable to execute code using any selected one of a plurality of different instruction sets, each set being configured for performing operations according to a respective one of the radio access technologies. The device is operable to dynamically switch between the radio access technologies, by selecting corresponding code for execution by the processor and selecting the corresponding instruction set for use in execution of the selected code.Type: ApplicationFiled: November 12, 2008Publication date: December 2, 2010Applicant: ICERA INC.Inventors: Simon Fellows, Simon Huckett, Godfrey Da Costa
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Patent number: 7143212Abstract: A modem architecture and a method of reducing on-chip memory requirements in a downloadable modem architecture are provided. The preferred architecture consists of a Digital Signal Processor (DSP) (6) with on-chip Random Access Memory (RAM) (12). A procedure which exploits inactivity intervals in a modem modulation function is provided. The procedure dynamically downloads the requisite code segments for each phase of the function from a cheaper, slower external memory (14) into the DSP on-chip RAM during inactivity intervals, thereby reducing the DSP on-chip RAM requirements.Type: GrantFiled: October 26, 1998Date of Patent: November 28, 2006Assignee: STMicroelectronics Asia Pacific (PTE) Ltd.Inventors: Pratima Pai, Godfrey Da Costa, Foo Yuen Leong
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Patent number: 7016428Abstract: A method and apparatus for efficient implementation of a frame-based trellis spectral shaping with a variable look-ahead depth that reduces memory and computational requirements that includes a data encoder for generating spectrally-shaped coded data according to a trellis coding system, a metric computation and trellis engine, and a processing circuit to apply a selected coding strategy to data frames to generate spectrally-shaped coded data form transmission.Type: GrantFiled: November 14, 1998Date of Patent: March 21, 2006Assignee: STMicroelectronics Asia Pacific PTE Ltd.Inventors: Pratima Pai, Godfrey Da Costa