Abstract: The present disclosure relates to a semiconductor device comprising a metallisation stack. The metallisation stack may include a first metallisation layer and a second metallisation layer. The first metallisation layer may be electrically connected to the second metallisation layer by a two or more stacked inter-metal vias.

Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.

Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.

Abstract: An apparatus includes a first inductive component connected in series with a first signal line of a differential signal path and configured to suppress residual electrostatic discharge (ESD) current spikes on the first signal line by using a first effective inductance. A second inductive component is connected in series to a second signal line of the differential signal path configured to suppress residual ESD current spikes on a second signal line of the differential signal path by using a second effective inductance. The first and second inductive components are configured to pass differential signals on the differential signal path by using inductive coupling between the first and second inductive components to provide a third effective inductance.

Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.

Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection device. The electrostatic discharge protection device, may comprise: a semiconductor controlled rectifier; and a p-n diode. The semiconductor controlled rectifier and the diode may be integrally disposed laterally at a major surface of a semiconductor substrate; and a current path for the semiconductor controlled rectifier may be separate from a current path for the diode.

Abstract: A semiconductor device (300a) comprising: a substrate (302) having a first surface (303); an n-type well (304) extending from the first surface (303) into the substrate (302) and configured to form a depletion region (306) in the substrate (302) around the n-type well (304); an insulating layer (340) extending over the first surface (303) of the substrate (302) from the n-type well (304), the insulating layer (340) configured to form an inversion layer (342) in the substrate (302) extending from the n-type well (304) adjacent to the first surface (303); wherein a p-type floating channel stopper (370a) is provided, configured to extend through the inversion layer (342) to reduce electrical coupling between the n-type well (304) and at least part of the inversion layer (342), and is electrically disconnected from a remainder of the substrate (320) outside of the depletion region (306).

Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection device. The electrostatic discharge protection device, may comprise: a semiconductor controlled rectifier; and a p-n diode. The semiconductor controlled rectifier and the diode may be integrally disposed laterally at a major surface of a semiconductor substrate; and a current path for the semiconductor controlled rectifier may be separate from a current path for the diode.

Abstract: The present disclosure relates to a semiconductor device comprising a metallisation stack. The metallisation stack may include a first metallisation layer and a second metallisation layer. The first metallisation layer may be electrically connected to the second metallisation layer by a two or more stacked inter-metal vias.

Abstract: A semiconductor device (300a) comprising: a substrate (302) having a first surface (303); an n-type well (304) extending from the first surface (303) into the substrate (302) and configured to form a depletion region (306) in the substrate (302) around the n-type well (304); an insulating layer (340) extending over the first surface (303) of the substrate (302) from the n-type well (304), the insulating layer (340) configured to form an inversion layer (342) in the substrate (302) extending from the n-type well (304) adjacent to the first surface (303); wherein a p-type floating channel stopper (370a) is provided, configured to extend through the inversion layer (342) to reduce electrical coupling between the n-type well (304) and at least part of the inversion layer (342), and is electrically disconnected from a remainder of the substrate (320) outside of the depletion region (306).