Patents by Inventor Goe-Sung Chae

Goe-Sung Chae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080166829
    Abstract: According to an embodiment, a fabrication method includes forming a gate line disposed along a first direction and a common line parallel to the gate line on a substrate, the gate and common lines spaced apart from each other, forming a gate insulating layer on the gate and common lines, forming a semiconductor layer on the gate insulating layer, forming a source electrode and a pixel electrode of transparent conductive material, the pixel electrode including a drain electrode portion, the drain electrode portion overlapping the semiconductor layer, forming a passivation layer including a first contact hole and an open portion, the first contact hole exposing the source electrode and the open portion exposing the pixel electrode, respectively, and forming a data line disposed along a second direction on the passivation layer, the data line connected to the source electrode through the first contact hole and crossing the gate line.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 10, 2008
    Inventors: Goe-Sung Chae, Jae-Kyun Lee, Yong-Sup Hwang
  • Patent number: 7333161
    Abstract: An array substrate includes a substrate, a gate line disposed along a first direction on the substrate, and a common line is parallel to the gate line, the common line being of the same material as the gate line. A gate insulating layer is on the gate and common lines, a semiconductor layer is on the gate insulating layer and a transparent pixel electrode includes a drain electrode portion. The drain electrode portion overlaps the semiconductor. A passivation layer includes a first contact hole and an open portion over the pixel and source electrodes, the first contact hole exposing the source electrode and the open portion exposing the pixel electrode, respectively. A data line is disposed along a second direction on the passivation layer, and the data line connected to the source electrode through the first contact hole and crossing the gate line.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: February 19, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Goe-Sung Chae, Jae-Kyun Lee, Yong-Sup Hwang