Abstract: There is provided a generator generating power from vibration, capable of increasing a power generation voltage even if the vibration is small in amplitude to thereby enhance efficiency of power generation. A vibration power generator, provided with a mechanism for converting vibrational energy into electrical energy, comprises a switch for switching over whether or not power is outputted, and control of the switch is executed by periodic control thereof such that switchover occurs between respective time periods for outputting the power and respective time periods for not outputting the power at cycles not less than twice and not more than 100 times cycles of vibration. With the invention, efficiency of the generator can be enhanced, and it is possible to provide electronic equipment without power supply from outside, and capable of saving trouble of battery replacement.

Abstract: In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.

Abstract: A semiconductor integrated circuit device having a mechanism of compensating not only circuit operational speed but also variations in leakage current, which includes: a main circuit constructed with CMOS device, a delay monitor for simulating a critical path of the main circuit constructed by a CMOS and monitoring a delay of the path, a PN Vt balance compensation circuit for detecting a threshold voltage difference between a PMOS transistor and an NMOS transistor, and a well bias generating circuit for receiving outputs of the delay monitor and the PN Vt balance compensation circuit and applying a well bias to the delay monitor and the main circuit so as to compensate the operation speed of the delay monitor to a desired speed and reduce a threshold voltage difference between the PMOS and NMOS transistors.

Abstract: A semiconductor integrated circuit and power control method use one of a supply voltage of the circuit and a delay time of the circuit to control a substrate bias voltage applied to a substrate of an insulated gate field effect transistor. High speed operation, consuming a small amount of power, is achieved. A CMOS circuit has a widened operating voltage range, with reduced leak currents in a standby mode in a range of high supply voltage, reducing power consumption of the CMOS circuit, and increasing operating speed of the CMOS circuit in the range of low supply voltage.

Abstract: In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.

Abstract: In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.

Abstract: A body bias control system allows for independent design of a functional module, thereby reducing the burden of designing the module. The body bias control system provides a switch circuit having an area in which the body bias is controlled independently of its outside portion, for controlling the supply of body bias in the vicinity of the area. Preferably three types of switches are provided for switching the body bias to suitable levels for a standby mode, a mode of normal operation and a mode of high-speed operation.

Abstract: Disclosed is a semiconductor integrated circuit device having a control mechanism 11 for compensating not only circuit operational speed but also variations in leakage current, which includes: a main circuit 10 constructed by a CMOS; a delay monitor 21 for simulating a critical path of the main circuit 10 constructed by a CMOS and monitoring a delay of the path; a PN Vt balance compensation circuit 23 for detecting a threshold voltage difference between a PMOS transistor and an NMOS transistor; and a well bias generating circuit 25 for receiving outputs of the delay monitor 21 and the PN Vt balance compensation circuit 23 and applying a well bias to the delay monitor 21 and the main circuit 10 so as to compensate the operation speed of the delay monitor 21 to a desired speed and reduce a threshold voltage difference between the PMOS and NMOS transistors.

Abstract: In a semiconductor integrated circuit device comprising a CMOS circuit, the CMOS circuit operating at a high speed, consuming a small amount of power, is achieved. In particular, acceleration of the operating speed under low voltage is achieved.

Abstract: Disclosed is a semiconductor integrated circuit device having a mechanism of compensating not only circuit operational speed but also variations in leakage current, which includes: a main circuit constructed by a CMOS; a delay monitor 11 for simulating a critical path of the main circuit constructed by a CMOS and monitoring a delay of the path; a PN Vt balance compensation circuit 13 for detecting a threshold voltage difference between a PMOS transistor and an NMOS transistor; and a well bias generating circuit 25 for receiving outputs of the delay monitor 11 and the PN Vt balance compensation circuit 15 and applying a well bias to the delay monitor 11 and the main circuit so as to compensate the operation speed of the delay monitor 11 to a desired speed and reduce a threshold voltage difference between the PMOS and NMOS transistors.

Abstract: In a semiconductor integrated circuit device comprising a CMOS circuit, the CMOS circuit operating at a high speed, consuming a small amount of power, is achieved. In particular, acceleration of the operating speed under low voltage is achieved. The semiconductor integrated circuit device of the invention comprises a main circuit including a CMOS circuit, a changeover circuit, a substrate bias control circuit and a switching circuit and, in accordance with a changing signal from the changeover circuit, switches states of a substrate of a MOS transistor of the main circuit between a state in which normal supply voltage as well as ground voltage are applied and a state in which forward bias is applied. The changeover circuit detects a drop in supply voltage, etc. and outputs changing signals.

Abstract: In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.

Abstract: In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit.

Abstract: In a semiconductor integrated circuit device comprising a CMOS circuit, the CMOS circuit operating at a high speed, consuming a small amount of power, is achieved. In particular, acceleration of the operating speed under low voltage is achieved.