Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a control device. The memory system includes a first device and first channels. The first channels are each connected to one or more second devices. The control device is connected to the first device via a second channel. The control device includes first circuits and a second circuit. The first circuits each execute data transfer to the second device as an access destination. The second circuit is provided between the first circuits and the second channel. The second circuit combines data from the first circuits and transfers the combined data to the second channel at a transfer rate higher than that of pre-combining data. The second circuit divides data received via the second channel and distributes pieces of divided data to the first circuits at a transfer rate lower than that of pre-dividing data.

Abstract: According to an embodiment, a semiconductor memory device includes a first chip, a second chip, and a third chip. The third chip is connected to the first chip via a first channel and connected to the second chip via a second channel. Upon receiving a first command sequence for data transfer from a first device, the third chip transfers a second command sequence for the data transfer to the first chip via the first channel and transfers a third command sequence for the data transfer to the second chip via the second channel. The first address includes a chip identification number of a value indicating the first chip. The second command sequence includes the first address. The third command sequence includes a second address obtained by replacing the value of the chip identification number in the first address indicating the first chip to a value indicating the second chip.

Abstract: A semiconductor storage device includes a plurality of semiconductor memory chips and a bridge chip. The bridge chip includes a first interface connectable to an external memory controller that is external to the semiconductor storage device, a plurality of second interfaces connected to the semiconductor memory chips, and a controller. The controller is configured to, upon receiving, by the first interface, a first command sequence that includes a data transfer command to perform data transfer with one of the semiconductor chips and size information indicating a size of data to be transferred, start an operation to perform the data transfer, and end the operation, upon an amount of data that has been received by the first interface during the data transfer reaching the size indicated by the size information.

Abstract: A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.

Abstract: A semiconductor storage device includes a bridge chip and memory chips connected to the bridge chip by a plurality of channels. The bridge chip includes a first delay circuit for setting the start of a first timing signal for a first memory chip output via a first channel and a second delay circuit for setting the start of for second timing signal for a second memory chip output via a second channel. A controller on the bridge chip controls at least one of the first and second delay circuits to adjust the start time of at least one of the first and second timing signals such that data sequences from the first and second memory chips will be aligned in time. The controller combines the data sequence from the first memory chip with the data sequence from the second memory chip to generate an interleaved serial sequence.

Abstract: A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.

Abstract: A semiconductor memory device includes a plurality of first chips and a second chip. The second chip is connected to the first chips via M second channels. Upon receipt of first data via the first channel at a transfer rate N times higher than the transfer rate per a single second channel, the second chip transmits the first data to the N first chips in parallel via the N second channels by sorting the first data into N pieces in a unit of bus width of the first channel. Upon receipt of L pieces of third data in parallel from L of the M second channels, the second chip sequentially concatenates the L pieces of third data in a unit of bus width of the first channel and transmits the data via the first channel at the transfer rate L times higher the transfer rate per the single second channel.

Abstract: A semiconductor storage device includes a bridge chip and memory chips connected to the bridge chip by a plurality of channels. The bridge chip includes a first delay circuit for setting the start of a first timing signal for a first memory chip output via a first channel and a second delay circuit for setting the start of for second timing signal for a second memory chip output via a second channel. A controller on the bridge chip controls at least one of the first and second delay circuits to adjust the start time of at least one of the first and second timing signals such that data sequences from the first and second memory chips will be aligned in time. The controller combines the data sequence from the first memory chip with the data sequence from the second memory chip to generate an interleaved serial sequence.

Abstract: A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.

Abstract: According to one embodiment, a transceiver includes a sampler, a pipeline, and a transmission circuit. The sampler takes a data signal received from a host at a timing based on a data strobe signal received from the host. The pipeline transfers the data signal taken by the sampler using at least a clock signal, different from the data strobe signal, as a drive signal. The transmission circuit acquires and transmits a data signal having passed through the pipeline.

Abstract: According to one embodiment, a transceiver includes a sampler, a pipeline, and a transmission circuit. The sampler takes a data signal received from a host at a timing based on a data strobe signal received from the host. The pipeline transfers the data signal taken by the sampler using at least a clock signal, different from the data strobe signal, as a drive signal. The transmission circuit acquires and transmits a data signal having passed through the pipeline.

Abstract: A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.

Abstract: The proposed variable length coder can detect the start codes appropriately, while reducing the circuit scale thereof.