Abstract: A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.

Abstract: An example operation may include one or more of identifying an expiration date associated with an asset, creating a blockchain transaction identifying the asset and the expiration date, storing the blockchain transaction on a blockchain, identifying a requesting entity with a certificate permitting access to the asset, and providing the requesting entity with access to the asset provided the expiration date is still pending.

Abstract: A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.

Abstract: A flash translation layer method, system, and computer program product, include sending a request with a type of feature and a flash characteristic of a translation table for a Solid-State disk, receiving, via a meta-flash translation layer (meta-FTL), the request and checking for a number of free blocks in a NAND chip, and instantiating a range in the NAND chip including the number of free blocks using the meta-FTL to create a compatible range of blocks for the type of feature and the flash characteristic of the translation table if the checking returns a confirmation that the number of free blocks is available.

Abstract: An example operation may include one or more of identifying an expiration date associated with an asset, creating a blockchain transaction identifying the asset and the expiration date, storing the blockchain transaction on a blockchain, identifying a requesting entity with a certificate permitting access to the asset, and providing the requesting entity with access to the asset provided the expiration date is still pending.

Abstract: A flash translation layer method, system, and computer program product, include sending a request with a type of feature and a flash characteristic of a translation table for a Solid-State disk, receiving, via a meta-flash translation layer (meta-FTL), the request and checking for a number of free blocks in a NAND chip, and instantiating a range in the NAND chip including the number of free blocks using the meta-FTL to create a compatible range of blocks for the type of feature and the flash characteristic of the translation table if the checking returns a confirmation that the number of free blocks is available.

Abstract: A method includes receiving a write request on at least one storage device; detecting a predetermined block of data within the write request; setting a first short code within a translation table if the predetermined block of data is detected; and writing the write request into the at least one storage device if the predetermined block of data is not detected.

Abstract: Accesses to logical pages of memory are monitored. Each logical page corresponds to a logical memory address and the accesses defining an access pattern. The logical memory addresses are logged in ordered pairs of consecutive logical pages in the access pattern. Upon receipt of a request to write data to a given logical page, a given ordered pair of consecutive logical pages containing the logical memory address of the given logical page as a first logical memory address in the ordered pair of logical memory addresses associated with that consecutive pair is obtained. A first physical memory address mapping to the first logical memory address is identified, and a second logical memory address from that identified consecutive pair. A second physical memory address mapping to the second logical memory address is identified, and the data and the second physical memory address are written to the first physical memory address.

Abstract: A method includes receiving a write request on at least one storage device; detecting a predetermined block of data within the write request; setting a first short code within a translation table if the predetermined block of data is detected; and writing the write request into the at least one storage device if the predetermined block of data is not detected.

Abstract: Accesses to logical pages of memory are monitored. Each logical page corresponds to a logical memory address and the accesses defining an access pattern. The logical memory addresses are logged in ordered pairs of consecutive logical pages in the access pattern. Upon receipt of a request to write data to a given logical page, a given ordered pair of consecutive logical pages containing the logical memory address of the given logical page as a first logical memory address in the ordered pair of logical memory addresses associated with that consecutive pair is obtained. A first physical memory address mapping to the first logical memory address is identified, and a second logical memory address from that identified consecutive pair. A second physical memory address mapping to the second logical memory address is identified, and the data and the second physical memory address are written to the first physical memory address.