Abstract: Applications can be automatically grouped in a secure workspace environment. An application organizer service can be deployed on a user computing device to intelligently group applications within secure workspaces based on resource requirements, peripheral usage, threat level and/or data sharing characteristics of the applications. The application organizer service may determine these characteristics in a variety of ways including through the monitoring of the applications as they execute inside the secure workspaces.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive a configuration message configuring the UE to communicate coordinated transmissions with multiple transmission reception points (TRPs) using a first coordinated transmission mode of a set of different coordinated transmission modes. The UE may receive, based on the configuration message, downlink control information including at least one indicator and receive a first coordinated transmission communicated in accordance with the first coordinated transmission mode. The UE may transmit, in accordance with a feedback configuration corresponding to the at least one indicator and the first coordinated transmission mode, a feedback message for the first coordinated transmission to at least one of the multiple TRPs.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Abstract: A semiconductor device is disclosed including one or more integrated memory modules. Each integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the first die may be flip-chip bonded to the second die.

Abstract: An apparatus includes a controller die and a group of dies that communicate with each other via a transmission line. Less than all of the dies of the group includes a respective on-die termination resistance circuit coupled to the transmission line. In some embodiments, one of the dies that includes an on-die termination resistance circuit is an end die of the group. In particular embodiments, the end die is the only die of the group that includes an on-die termination resistance circuit coupled to the transmission line. Transmission frequencies or data rates may be increased without degrading signal quality by removing capacitance associated with on-die termination resistance circuits from at least one of the dies of the group.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Abstract: An apparatus includes a controller die and a group of dies that communicate with each other via a transmission line. Less than all of the dies of the group includes a respective on-die termination resistance circuit coupled to the transmission line. In some embodiments, one of the dies that includes an on-die termination resistance circuit is an end die of the group. In particular embodiments, the end die is the only die of the group that includes an on-die termination resistance circuit coupled to the transmission line. Transmission frequencies or data rates may be increased without degrading signal quality by removing capacitance associated with on-die termination resistance circuits from at least one of the dies of the group.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Abstract: A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.

Abstract: A semiconductor device is disclosed including one or more integrated memory modules. Each integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the first die may be flip-chip bonded to the second die.

Abstract: An apparatus may include a controller die configured to communicate with a plurality of dies via a transmission line. The controller die may be configured to transmit a signal on the transmission line to a target die of the plurality of dies, or the target die may transmit a signal on the transmission line. The transmission may be dependent on an end die of the plurality of dies setting an end-die termination resistance to a low level. In situations where the target memory is receiving the signal, the target die may set target an on-die termination resistance to a high level. In situations where the target memory die is transmitting the signal, the target die may set an on-die termination resistance to a low level.

Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.

Abstract: An apparatus may include a controller die configured to communicate with a plurality of dies via a transmission line. The controller die may be configured to transmit a signal on the transmission line to a target die of the plurality of dies, or the target die may transmit a signal on the transmission line. The transmission may be dependent on an end die of the plurality of dies setting an end-die termination resistance to a low level. In situations where the target memory is receiving the signal, the target die may set target an on-die termination resistance to a high level. In situations where the target memory die is transmitting the signal, the target die may set an on-die termination resistance to a low level.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: In one embodiment, a method for transferring digital files is provided. The method includes: downloading an application for facilitating the transfer of used digital files; storing the application at the client; receiving an indication of a used digital file that a user desires to sell; searching, using the application, storage on the client to determine any instances of the digital file; deleting any instances of the digital file if they are determined; transferring a forwarded file of the used digital file to a second entity; and deleting, using the application, the used digital file from the client upon transfer of the forwarded file.