Patents by Inventor Gokul Malyavanatham
Gokul Malyavanatham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240112951Abstract: Integrated circuit interconnect structures including a niobium-based barrier material. In some embodiments, a layer of essentially niobium may be sputter deposited, for example to a thickness of less than 8 nm at a bottom of an interconnect via. A copper-based fill material may then be deposited over the niobium barrier material. Integrated circuit interconnect metallization may comprise some layers of metallization that have a tantalum-based barrier and other layers of metallization that have a niobium-based barrier.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Philip Yashar, Gokul Malyavanatham, Hema Vijwani
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Patent number: 11430944Abstract: An apparatus includes a first interconnect structure above a substrate, a memory device above and coupled with the first interconnect structure in a memory region. The memory device includes a non-volatile memory element, an electrode on the non-volatile memory element, and a metallization structure on a portion of the electrode. The apparatus further includes a second interconnect structure in a logic region above the substrate, where the second interconnect structure is laterally distant from the first interconnect structure. The logic region further includes a second metallization structure coupled to the second interconnect structure and a conductive structure between the second metallization structure and the second interconnect structure. The apparatus further includes a dielectric spacer that extends from the memory device to the conductive structure.Type: GrantFiled: March 19, 2019Date of Patent: August 30, 2022Assignee: INTEL CORPORATIONInventors: Christopher Wiegand, Gokul Malyavanatham, Oleg Golonzka
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Publication number: 20220157735Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.Type: ApplicationFiled: January 27, 2022Publication date: May 19, 2022Inventors: Flavio GRIGGIO, Philip YASHAR, Anthony V. MULE, Gopinath TRICHY, Gokul MALYAVANATHAM
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Patent number: 11270943Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.Type: GrantFiled: March 27, 2018Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Flavio Griggio, Philip Yashar, Anthony V. Mule, Gopinath Trichy, Gokul Malyavanatham
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Publication number: 20220068802Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a first conductive interconnect line in a first inter-layer dielectric (ILD) layer above a substrate, a second conductive interconnect line in a second ILD layer above the first ILD layer, and a conductive via coupling the first conductive interconnect line and the second conductive interconnect line, the conductive via having a single, nitrogen-free tantalum (Ta) barrier layer. In another example, a method of fabricating an integrated circuit structure includes forming a partial trench in an inter-layer dielectric (ILD layer, the ILD layer on an etch stop layer, etching a hanging via that lands on the etch stop layer, and performing a breakthrough etch through the etch stop layer to form a trench and via opening in the ILD layer and the etch stop layer.Type: ApplicationFiled: December 23, 2020Publication date: March 3, 2022Inventors: Atul MADHAVAN, Gokul MALYAVANATHAM, Philip YASHAR, Mark KOEPER, Bharath BANGALORE RAJEEVA, Krishna T. MARLA, Umang DESAI, Harry B. RUSSELL
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Publication number: 20200303623Abstract: An apparatus includes a first interconnect structure above a substrate, a memory device above and coupled with the first interconnect structure in a memory region. The memory device includes a non-volatile memory element, an electrode on the non-volatile memory element, and a metallization structure on a portion of the electrode. The apparatus further includes a second interconnect structure in a logic region above the substrate, where the second interconnect structure is laterally distant from the first interconnect structure. The logic region further includes a second metallization structure coupled to the second interconnect structure and a conductive structure between the second metallization structure and the second interconnect structure. The apparatus further includes a dielectric spacer that extends from the memory device to the conductive structure.Type: ApplicationFiled: March 19, 2019Publication date: September 24, 2020Applicant: Intel CorporationInventors: Christopher WIEGAND, Gokul MALYAVANATHAM, Oleg GOLONZKA
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Publication number: 20200105669Abstract: A semiconductor structure is disclosed. The semiconductor structure includes back end layers that include a first metallization layer, a second metallization layer, and a scalable resistor between the first metallization layer and the second metallization layer. The semiconductor structure also includes front end layers.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Sagar SUTHRAM, Seung-June CHOI, Vishal JAVVAJI, Soumya KAR, Ahmed ESMAIL, Gokul MALYAVANATHAM
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Patent number: 10446439Abstract: An embodiment includes an apparatus comprising: a transistor formed on a substrate; and a metal interconnect formed in a dielectric layer above the transistor, wherein: the interconnect comprises a copper layer and a barrier layer that separates the copper layer from the dielectric layer, and the barrier layer comprises tantalum and niobium. Other embodiments are described herein.Type: GrantFiled: December 26, 2015Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Philip Yashar, Gokul Malyavanatham
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Publication number: 20190304918Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.Type: ApplicationFiled: March 27, 2018Publication date: October 3, 2019Applicant: INTEL CORPORATIONInventors: Flavio Griggio, Philip Yashar, Anthony V. Mule, Gopinath Trichy, Gokul Malyavanatham
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Publication number: 20180301373Abstract: An embodiment includes a transmitter comprising: an oxide layer between a substrate and an epitaxial silicon layer; a modulator included within the silicon layer and a hybrid laser on the silicon layer; wherein (a) the silicon layer is thinner directly adjacent the modulator than directly adjacent the laser; and (b) the silicon layer comprises gratings directly under the laser and directly contacting the oxide layer. Other embodiments are described herein.Type: ApplicationFiled: December 26, 2015Publication date: October 18, 2018Applicant: Intel CorporationInventors: Philip Yashar, Gokul Malyavanatham