Patents by Inventor Gokul Subramanian Ravi

Gokul Subramanian Ravi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11868809
    Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: January 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Muhammad Amber Hassaan, Anirudh Mohan Kaushik, Sooraj Puthoor, Gokul Subramanian Ravi, Bradford Beckmann, Ashwin Aji
  • Patent number: 11734059
    Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: August 22, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Muhammad Amber Hassaan, Anirudh Mohan Kaushik, Sooraj Puthoor, Gokul Subramanian Ravi, Bradford Beckmann, Ashwin Aji
  • Publication number: 20230229494
    Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 20, 2023
    Inventors: Muhammad Amber HASSAAN, Anirudh Mohan KAUSHIK, Sooraj PUTHOOR, Gokul Subramanian RAVI, Bradford BECKMANN, Ashwin AJI
  • Publication number: 20210294646
    Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 23, 2021
    Inventors: Muhammad Amber HASSAAN, Anirudh Mohan KAUSHIK, Sooraj PUTHOOR, Gokul Subramanian RAVI, Bradford BECKMANN, Ashwin AJI
  • Patent number: 10831232
    Abstract: A computer architecture suitable for out-of-order processors manages the problem of timing slack, in which an instruction completes before its clock cycle, by recycling that slack to allow the next succeeding instruction allowing that instruction to begin execution earlier. This recycling mechanism is enabled through the use of a transparent gating between execution units which allows data transfer before clock cycle boundaries and, in some cases, by aggressively issuing children instructions contemporaneously with their parent instruction after a grandparent instruction is issued.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 10, 2020
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Gokul Subramanian Ravi, Mikko H. Lipasti
  • Publication number: 20200264652
    Abstract: A computer architecture suitable for out-of-order processors manages the problem of timing slack, in which an instruction completes before its clock cycle, by recycling that slack to allow the next succeeding instruction allowing that instruction to begin execution earlier. This recycling mechanism is enabled through the use of a transparent gating between execution units which allows data transfer before clock cycle boundaries and, in some cases, by aggressively issuing children instructions contemporaneously with their parent instruction after a grandparent instruction is issued.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Gokul Subramanian Ravi, Mikko H. Lipasti