Patents by Inventor Golam R. Chowdhury
Golam R. Chowdhury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9074942Abstract: A method and apparatus for determining a temperature of a semiconductor device is provided herein. One aspect of the disclosed subject matter is seen in a temperature sensing device. The temperature sensing device comprises a diode and a circuit. The diode is adapted to be reverse biased by a charging voltage applied thereto. The circuit determines a temperature of the diode based on a rate that the voltage on the diode discharges in response to the charging voltage being uncoupled from the diode.Type: GrantFiled: September 10, 2013Date of Patent: July 7, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Golam R. Chowdhury, Arjang Hassibi
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Publication number: 20140016669Abstract: A method and apparatus for determining a temperature of a semiconductor device is provided herein. One aspect of the disclosed subject matter is seen in a temperature sensing device. The temperature sensing device comprises a diode and a circuit. The diode is adapted to be reverse biased by a charging voltage applied thereto. The circuit determines a temperature of the diode based on a rate that the voltage on the diode discharges in response to the charging voltage being uncoupled from the diode.Type: ApplicationFiled: September 10, 2013Publication date: January 16, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Golam R. Chowdhury, Arjang Hassibi
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Patent number: 8573841Abstract: A method and apparatus for determining a temperature of a semiconductor device is provided herein. One aspect of the disclosed subject matter is seen in a temperature sensing device. The temperature sensing device comprises a diode and a circuit. The diode is adapted to be reverse biased by a charging voltage applied thereto. The circuit determines a temperature of the diode based on a rate that the voltage on the diode discharges in response to the charging voltage being uncoupled from the diode.Type: GrantFiled: April 8, 2011Date of Patent: November 5, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Golam R. Chowdhury, Arjang Hassibi
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Patent number: 8410833Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.Type: GrantFiled: March 30, 2011Date of Patent: April 2, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Michael A. Nix, Golam R. Chowdhury, Curtis M. Brody, Faisal A. Syed
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Publication number: 20120257650Abstract: A method and apparatus for determining a temperature of a semiconductor device is provided herein. One aspect of the disclosed subject matter is seen in a temperature sensing device. The temperature sensing device comprises a diode and a circuit. The diode is adapted to be reverse biased by a charging voltage applied thereto. The circuit determines a temperature of the diode based on a rate that the voltage on the diode discharges in response to the charging voltage being uncoupled from the diode.Type: ApplicationFiled: April 8, 2011Publication date: October 11, 2012Inventor: Golam R. Chowdhury
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Publication number: 20120218012Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.Type: ApplicationFiled: March 30, 2011Publication date: August 30, 2012Inventors: Michael A. Nix, Golam R. Chowdhury, Curtis M. Brody, Faisal A. Syed
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Patent number: 8041975Abstract: The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.Type: GrantFiled: May 13, 2008Date of Patent: October 18, 2011Assignee: Silicon Laboratories Inc.Inventors: Biranchinath Sahu, Douglas F. Pastorello, Golam R. Chowdhury
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Patent number: 8010819Abstract: A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.Type: GrantFiled: October 21, 2008Date of Patent: August 30, 2011Assignee: Silicon LaboratoriesInventors: Douglas F. Pastorello, Douglas Holberg, William Gene Durbin, Biranchinath Sahu, Golam R. Chowdhury
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Patent number: 7746262Abstract: A method for coding a digital to analog converter of a successive approximation register analog to digital converter includes the steps of first switching capacitors associated with a bit from ground to a reference voltage. Next, a determination is made of whether a logical value of the bit is a first or a second value. If the logical value is the first value, capacitors associated with a next bit are switched from ground to a reference voltage. If the logical value is the second value, one half of the capacitors associated with the bit currently connected are switched from the reference voltage to ground.Type: GrantFiled: December 19, 2005Date of Patent: June 29, 2010Assignee: Silicon Laboratories Inc.Inventors: Golam R. Chowdhury, Douglas S. Piasecki, Bruce Del Signore, Kevin Kwak
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Publication number: 20100079439Abstract: Charge pump circuitry comprises a voltage for generating a first regulated voltage. A low drop out regulator generates a second regulated voltage responsive to the first regulated voltage. A charge pump voltage generation circuit generates a voltage. First and second resistor strings are responsive to the generated voltage. The first resistor string provides a first plurality of bias voltages to an LCD responsive to the voltage in a first mode of operation and the second resistor string provides faster charging and discharging of the connected LCD elements responsive to a second mode of operation.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: SILICON LABORATORIES INC.Inventors: FARRIS BAR, GOLAM R. CHOWDHURY, DOUGLAS PIASECKI, THOMAS S. DAVID
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Publication number: 20090187773Abstract: A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.Type: ApplicationFiled: October 21, 2008Publication date: July 23, 2009Applicant: SILICON LABORATORIES INC.Inventors: DOUGLAS F. PASTORELLO, DOUGLAS HOLBERG, WILLIAM GENE DURBIN, BIRANCHINATH SAHU, GOLAM R. CHOWDHURY
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Patent number: 7441131Abstract: A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.Type: GrantFiled: September 30, 2005Date of Patent: October 21, 2008Assignee: Silicon Laboratories Inc.Inventors: Douglas F. Pastorello, Douglas Holberg, William Gene Durbin, Biranchinath Sahu, Golam R. Chowdhury
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Publication number: 20080246526Abstract: The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.Type: ApplicationFiled: May 13, 2008Publication date: October 9, 2008Applicant: SILICON LABORATORIES INC.Inventors: BIRANCHINATH SAHU, DOUGLAS F. PASTORELLO, GOLAM R. CHOWDHURY
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Patent number: 7382181Abstract: A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.Type: GrantFiled: January 16, 2007Date of Patent: June 3, 2008Assignee: Silicon Laboratories Inc.Inventors: Golam R. Chowdhury, Douglas R. Holberg
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Patent number: 7373533Abstract: The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.Type: GrantFiled: September 30, 2005Date of Patent: May 13, 2008Assignee: Silicon LaboratoriesInventors: Biranchinath Sahu, Douglas F. Pastorello, Golam R. Chowdhury
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Publication number: 20070139243Abstract: A method for coding a digital to analog converter of a successive approximation register analog to digital converter includes the steps of first switching capacitors associated with a bit from ground to a reference voltage. Next, a determination is made of whether a logical value of the bit is a first or a second value. If the logical value is the first value, capacitors associated with a next bit are switched from ground to a reference voltage. If the logical value is the second value, one half of the capacitors associated with the bit currently connected are switched from the reference voltage to ground.Type: ApplicationFiled: December 19, 2005Publication date: June 21, 2007Applicant: SILICON LABORATORIES, INC.Inventors: Golam R. Chowdhury, Douglas S. Piasecki, Kevin Kwak, Bruce Del Signore
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Patent number: 7199746Abstract: The method is described for selecting capacitors from a capacitor array for each bit of a SAR ADC. The process involves selecting a group of capacitors from the capacitor array and determining a weight of the selected group of capacitors. A determination is made if the weights of the selected group of capacitors are substantially equal to their desired values. If the weights are substantially equal to their desired values, the selected group of capacitors is associated with each bit of the SAR ADC. If the weights are not substantially equal to their desired values, a next group of capacitors from the capacitor array is selected for the bits. This process of selecting a group of capacitors and determining their weights is repeated until determined weight for a group of capacitors equals or is closest to the desired values.Type: GrantFiled: December 19, 2005Date of Patent: April 3, 2007Assignee: Silicon Laboratories Inc.Inventors: Golam R. Chowdhury, Douglas Piasecki
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Patent number: 7187319Abstract: A sampling network comprises analog comparator for comparing an analog voltage to a plurality of successive voltage inputs. A plurality of capacitors are connected in parallel with a first end of each of the capacitors coupled to the first input of the analog comparator to provide one of the successive voltage inputs. A first plurality of switches includes one switch associated with each of the plurality of capacitors to connect an input voltage to the second end of the capacitor. A bulk of a switch of the first plurality of switches is connected to the input voltage while the input voltage is being sampled and to a power supply voltage while the reference voltage is being sampled. A second plurality of switches is in parallel with the first plurality of switches and further includes one switch connected to each of the plurality of capacitors. The second plurality of switches connect a reference voltage to a second end of the capacitor.Type: GrantFiled: September 29, 2005Date of Patent: March 6, 2007Assignee: Silicon Laboratories Inc.Inventor: Golam R. Chowdhury
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Patent number: 7164311Abstract: A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.Type: GrantFiled: September 30, 2004Date of Patent: January 16, 2007Assignee: Silicon Laboratories Inc.Inventors: Golam R. Chowdhury, Douglas R. Holberg