Abstract: Methods and apparatus for a Latent Supplementary Protocol (LSP) for enhancing performance and functionality of communication systems. The LSP implements a PAM (Pulse Amplitude Modulation) 6 (PAM6) modulation scheme utilizing 36 constellation points comprising a multiplex of 32-QAM and shifted 32-QAM constellations, each comprising 32 PAM6 symbols. Supplementary data are added to constellation points comprising conveyors and shifted constellation points without affecting the bandwidth of transfer of payload data between link partners implementing the LSP. The supplementary data may be employed for various purposes, including but not limited to payload data protection, an auxiliary communication channel between link partners, and transfer of additional payload data.

Abstract: Methods and apparatus to compensate for post-training insertion loss variation. Receiver Physical Layer (PHY) circuitry for each receive lane in a link comprising a chain of equalizer components including a Variable Gain Amplifier (VGA). In conjunction with initial link training, the VGA gain is set based on an initial temperature. During link training, one or more of the equalizer components are adjusted to obtain link convergence, followed by transitioning to a “link up” phase under which data transmission and reception begin. While operating in the link up phase, one or more of the equalizer components are adjusted in response to changes in interconnect insertion loss to maintain operation of the link within a link margin. The method may be implemented in various types of links including but not limited to Ethernet, PCIe, CXL, and UPI links.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.