Patents by Inventor Golan Zeituni

Golan Zeituni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10594967
    Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: March 17, 2020
    Assignee: Sony Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Publication number: 20190356874
    Abstract: A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.
    Type: Application
    Filed: August 8, 2018
    Publication date: November 21, 2019
    Inventors: Noam Eshel, Golan Zeituni
  • Publication number: 20190356877
    Abstract: An image sensor comprises a plurality of image pixel circuits arranged in an array; image processing circuitry including a sample-and-hold circuit configured to receive a first reference voltage and an analog-to-digital converter configured to receive a second reference voltage; and a reference adjustment circuit configured to selectively adjust the first reference voltage and/or the second reference voltage, thereby to match an operating range of the sample-and-hold circuit with an operating range of the analog-to-digital converter, based on a measurement signal.
    Type: Application
    Filed: August 14, 2018
    Publication date: November 21, 2019
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 10462397
    Abstract: A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: October 29, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 10051224
    Abstract: An image processing circuit includes a first dual sample-and-hold circuit that samples a first data and a second data from a first pixel, a second dual sample-and-hold circuit that samples a third data and a fourth data from a second pixel, a voltage-to-current circuit including a resistor and a current source, that receives the first data and the second data to output a first difference data, and that receives the third data and the fourth data to output a second difference data; and an analog-to-digital converter that converts the first and second difference data from an analog form to a digital form.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: August 14, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 10026497
    Abstract: A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: July 17, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni, Zvika Lupu
  • Patent number: 10008283
    Abstract: A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: June 26, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Amit Sokolover, Golan Zeituni
  • Publication number: 20180160063
    Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
    Type: Application
    Filed: February 2, 2018
    Publication date: June 7, 2018
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 9930274
    Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 27, 2018
    Assignee: Sony Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Publication number: 20180007294
    Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 9826180
    Abstract: An image processing circuit comprises a first sample-and-hold circuit that samples a first data from a pixel; a second sample-and-hold circuit that samples a second data from the pixel; a voltage-to-current circuit that includes a resistor and a current source, and receives the first data and the second data to output a difference data; and a black sun spot determination circuit. The black sun spot determination circuit compares a first VSL level at a first time with a second VSL level at a second time, both from the second sample-and-hold circuit, and determines the presence of a black sun spot based on a difference between the first and second level.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 21, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Publication number: 20170323686
    Abstract: A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.
    Type: Application
    Filed: July 7, 2017
    Publication date: November 9, 2017
    Inventors: NOAM ESHEL, GOLAN ZEITUNI, ZVIKA LUPU
  • Publication number: 20170309347
    Abstract: A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 26, 2017
    Inventors: Noam Eshel, Amit Sokolover, Golan Zeituni
  • Patent number: 9728271
    Abstract: A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: August 8, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni, Zvika Lupu
  • Patent number: 9715941
    Abstract: A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 25, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Amit Sokolover, Golan Zeituni
  • Patent number: 9661251
    Abstract: An image processing circuit includes a first sample-and-hold circuit that samples a first data from a pixel, a second sample-and-hold circuit that samples a second data from the pixel, a voltage-to-current circuit that includes a resistor and a current source and receives the first and second data to output a difference data, an adaptive gain control determination circuit that determines whether a rate of change of a signal from the pixel exceeds a threshold based on an output of the second sample-and-hold circuit, and a current-mode ADC that converts the difference data from an analog form to a digital form.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 23, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Publication number: 20170126998
    Abstract: An image processing circuit comprises a first sample-and-hold circuit that samples a first data from a pixel; a second sample-and-hold circuit that samples a second data from the pixel; a voltage-to-current circuit that includes a resistor and a current source, and receives the first data and the second data to output a difference data; and a black sun spot determination circuit. The black sun spot determination circuit compares a first VSL level at a first time with a second VSL level at a second time, both from the second sample-and-hold circuit, and determines the presence of a black sun spot based on a difference between the first and second level.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Noam Eshel, Golan Zeituni
  • Publication number: 20170127002
    Abstract: An image processing circuit includes a first sample-and-hold circuit that samples a first data from a pixel, a second sample-and-hold circuit that samples a second data from the pixel, a voltage-to-current circuit that includes a resistor and a current source and receives the first and second data to output a difference data, an adaptive gain control determination circuit that determines whether a rate of change of a signal from the pixel exceeds a threshold based on an output of the second sample-and-hold circuit, and a current-mode ADC that converts the difference data from an analog form to a digital form.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Noam Eshel, Golan Zeituni
  • Publication number: 20170125123
    Abstract: A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Noam Eshel, Amit Sokolover, Golan Zeituni
  • Publication number: 20170125124
    Abstract: A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Noam Eshel, Golan Zeituni, Zvika Lupu