Patents by Inventor Golan Zeituni
Golan Zeituni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240155259Abstract: An image sensor assembly includes a pixel circuit including a charge storage structure and an amplification transistor. A load path of the amplification transistor is between an amplifier drain line and a pixel output node. A potential at a storage node of the charge storage structure controls the amplification transistor. An amplifier drain circuit is configured to pass a low potential to the amplifier drain line in a reset period and a high potential in a readout period. A transition from the low potential to the high potential is not before an end of the reset period and prior to a start of the readout period.Type: ApplicationFiled: February 17, 2022Publication date: May 9, 2024Applicant: Sony Semiconductor Solutions CorporationInventors: Noam ESHEL, Golan ZEITUNI
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Publication number: 20240107201Abstract: A pixel circuit (100) includes a photoelectric conversion circuit (110), an integration capacitor (Cint) and a supplementary circuit (120). The photoelectric conversion circuit (110) generates and outputs a photocurrent (Iphoto). The integration capacitor (Cint) includes a storage electrode (CintS) and a reference electrode (CintR), wherein the reference electrode (CintR) is connected to a first supply potential (VSUP1), and wherein the integration capacitor (Cint) is configured to integrate the photocurrent on the storage electrode (CintS) in an integration period (Tint). The supplementary circuit (120) pre-charges a working node (WN) between the photoelectric conversion circuit (110) and the storage electrode (CintS) to a pre-charge potential (Vpre) that differs from the first supply potential (VSUP1).Type: ApplicationFiled: February 17, 2022Publication date: March 28, 2024Applicant: Sony Semiconductor Solutions CorporationInventors: Golan ZEITUNI, Noam Zeev ESHEL
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Publication number: 20240107202Abstract: A column signal processing unit includes a current control circuit (110) and a feedback circuit (120). The current control circuit (110) is electrically connected between a data signal line (VSL) and a supply reference potential (GND). The feedback circuit (120) is configured to reduce a capacitive load of the data signal line (VSL). A feedback path (121) of the feedback circuit (120) includes a series connection of a feedback capacitor (122) and a delay element (123), wherein the delay element (123) is configured to increase a time delay in the feedback path (121).Type: ApplicationFiled: February 17, 2022Publication date: March 28, 2024Applicant: Sony Semiconductor Solutions CorporationInventors: Golan ZEITUNI, Noam Zeev ESHEL
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Publication number: 20230232129Abstract: A time-of-flight device comprises a pixel array including an array of pixel circuits, wherein a column of the array includes: a first pixel circuit including a first photodiode, a first capacitor and a second capacitor coupled to the first photodiode, and a second pixel circuit including a second photodiode, a third capacitor and a fourth capacitor coupled to the second photodiode, a first signal line coupled to the first capacitor, a second signal line coupled to the second capacitor, a third signal line coupled to the third capacitor, a fourth signal line coupled to the fourth capacitor, a first switch circuitry, a second switch circuitry, a first comparator coupled to the first signal line and the third signal line through the first switch circuitry, and a second comparator coupled to the second signal line and the fourth signal line through the second switch circuitry.Type: ApplicationFiled: March 24, 2023Publication date: July 20, 2023Inventors: Zvika Veig, Golan Zeituni, Kei Nakagawa
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Patent number: 11641532Abstract: A time-of-flight device comprises a pixel array including an array of pixel circuits, wherein a column of the array includes: a first pixel circuit including a first photodiode, a first capacitor and a second capacitor coupled to the first photodiode, and a second pixel circuit including a second photodiode, a third capacitor and a fourth capacitor coupled to the second photodiode, a first signal line coupled to the first capacitor, a second signal line coupled to the second capacitor, a third signal line coupled to the third capacitor, a fourth signal line coupled to the fourth capacitor, a first switch circuitry, a second switch circuitry, a first comparator coupled to the first signal line and the third signal line through the first switch circuitry, and a second comparator coupled to the second signal line and the fourth signal line through the second switch circuitry.Type: GrantFiled: March 11, 2022Date of Patent: May 2, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Zvika Veig, Golan Zeituni, Kei Nakagawa
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Patent number: 11632513Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.Type: GrantFiled: October 21, 2021Date of Patent: April 18, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Yosuke Ueno, Golan Zeituni, Noam Eshel, Yusuke Ikeda, Kiyoshi Makigawa
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Publication number: 20220247951Abstract: A time-of-flight device comprises a pixel array including an array of pixel circuits, wherein a column of the array includes: a first pixel circuit including a first photodiode, a first capacitor and a second capacitor coupled to the first photodiode, and a second pixel circuit including a second photodiode, a third capacitor and a fourth capacitor coupled to the second photodiode, a first signal line coupled to the first capacitor, a second signal line coupled to the second capacitor, a third signal line coupled to the third capacitor, a fourth signal line coupled to the fourth capacitor, a first switch circuitry, a second switch circuitry, a first comparator coupled to the first signal line and the third signal line through the first switch circuitry, and a second comparator coupled to the second signal line and the fourth signal line through the second switch circuitry.Type: ApplicationFiled: March 11, 2022Publication date: August 4, 2022Inventors: Zvika Veig, Golan Zeituni, Kei Nakagawa
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Patent number: 11310455Abstract: An image sensor and electronic apparatus comprise a pixel circuit configured to generate an analog signal; a vertical signal line configured to convey the analog signal from the pixel circuit; an analog amplifier circuit configured to receive the analog signal via the vertical signal line and generate an amplified signal; and a tail current boost circuit configured to modify an instantaneous gain bandwidth product of the analog amplifier circuit by temporarily modifying a tail current of the analog amplifier circuit.Type: GrantFiled: January 17, 2020Date of Patent: April 19, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Golan Zeituni, Noam Eshel
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Patent number: 11297270Abstract: A time-of-flight device comprises a pixel array including an array of pixel circuits, wherein a column of the array includes: a first pixel circuit including a first photodiode, a first capacitor and a second capacitor coupled to the first photodiode, and a second pixel circuit including a second photodiode, a third capacitor and a fourth capacitor coupled to the second photodiode, a first signal line coupled to the first capacitor, a second signal line coupled to the second capacitor, a third signal line coupled to the third capacitor, a fourth signal line coupled to the fourth capacitor, a first switch circuitry, a second switch circuitry, a first comparator coupled to the first signal line and the third signal line through the first switch circuitry, and a second comparator coupled to the second signal line and the fourth signal line through the second switch circuitry.Type: GrantFiled: March 24, 2020Date of Patent: April 5, 2022Assignees: Sony Corporation, Sony Semiconductor Solutions CorporationInventors: Zvika Veig, Golan Zeituni, Kei Nakagawa
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Publication number: 20220046199Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.Type: ApplicationFiled: October 21, 2021Publication date: February 10, 2022Inventors: Yosuke Ueno, Golan Zeituni, Noam Eshel, Yusuke Ikeda, Kiyoshi Makigawa
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Patent number: 11178350Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.Type: GrantFiled: July 10, 2018Date of Patent: November 16, 2021Assignee: Sony Semiconductor Solutions CorporationInventors: Yosuke Ueno, Golan Zeituni, Noam Eshel, Yusuke Ikeda, Kiyoshi Makigawa
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Publication number: 20210227163Abstract: An image sensor and electronic apparatus comprise a pixel circuit configured to generate an analog signal; a vertical signal line configured to convey the analog signal from the pixel circuit; an analog amplifier circuit configured to receive the analog signal via the vertical signal line and generate an amplified signal; and a tail current boost circuit configured to modify an instantaneous gain bandwidth product of the analog amplifier circuit by temporarily modifying a tail current of the analog amplifier circuit.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: Golan Zeituni, Noam Eshel
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Publication number: 20210203868Abstract: A time-of-flight device comprises a pixel array including an array of pixel circuits, wherein a column of the array includes: a first pixel circuit including a first photodiode, a first capacitor and a second capacitor coupled to the first photodiode, and a second pixel circuit including a second photodiode, a third capacitor and a fourth capacitor coupled to the second photodiode, a first signal line coupled to the first capacitor, a second signal line coupled to the second capacitor, a third signal line coupled to the third capacitor, a fourth signal line coupled to the fourth capacitor, a first switch circuitry, a second switch circuitry, a first comparator coupled to the first signal line and the third signal line through the first switch circuitry, and a second comparator coupled to the second signal line and the fourth signal line through the second switch circuitry.Type: ApplicationFiled: March 24, 2020Publication date: July 1, 2021Inventors: Zvika Veig, Golan Zeituni, Kei Nakagawa
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Publication number: 20200244907Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.Type: ApplicationFiled: July 10, 2018Publication date: July 30, 2020Inventors: Yosuke Ueno, Golan Zeituni, Noam Eshel, Yusuke Ikeda, Kiyoshi Makigawa
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Patent number: 10594967Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.Type: GrantFiled: February 2, 2018Date of Patent: March 17, 2020Assignee: Sony CorporationInventors: Noam Eshel, Golan Zeituni
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Publication number: 20190356874Abstract: A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.Type: ApplicationFiled: August 8, 2018Publication date: November 21, 2019Inventors: Noam Eshel, Golan Zeituni
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Publication number: 20190356877Abstract: An image sensor comprises a plurality of image pixel circuits arranged in an array; image processing circuitry including a sample-and-hold circuit configured to receive a first reference voltage and an analog-to-digital converter configured to receive a second reference voltage; and a reference adjustment circuit configured to selectively adjust the first reference voltage and/or the second reference voltage, thereby to match an operating range of the sample-and-hold circuit with an operating range of the analog-to-digital converter, based on a measurement signal.Type: ApplicationFiled: August 14, 2018Publication date: November 21, 2019Inventors: Noam Eshel, Golan Zeituni
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Patent number: 10462397Abstract: A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.Type: GrantFiled: August 8, 2018Date of Patent: October 29, 2019Assignee: Sony Semiconductor Solutions CorporationInventors: Noam Eshel, Golan Zeituni
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Patent number: 10051224Abstract: An image processing circuit includes a first dual sample-and-hold circuit that samples a first data and a second data from a first pixel, a second dual sample-and-hold circuit that samples a third data and a fourth data from a second pixel, a voltage-to-current circuit including a resistor and a current source, that receives the first data and the second data to output a first difference data, and that receives the third data and the fourth data to output a second difference data; and an analog-to-digital converter that converts the first and second difference data from an analog form to a digital form.Type: GrantFiled: November 18, 2016Date of Patent: August 14, 2018Assignee: Sony Semiconductor Solutions CorporationInventors: Noam Eshel, Golan Zeituni
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Patent number: 10026497Abstract: A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.Type: GrantFiled: July 7, 2017Date of Patent: July 17, 2018Assignee: Sony Semiconductor Solutions CorporationInventors: Noam Eshel, Golan Zeituni, Zvika Lupu