Abstract: A programmable timing module generates a phase adjusted clock signal, suitable for use in a high speed bus system. In one embodiment, the programmable timing includes a signal generator, first and second modulators, and a combiner circuit. The signal generator generates first and second signals based on a clock signal, such that the first and second signals have a phase separation of about 90 degrees. The first modulator receives the first signal and a first modulation control signal, and generates a modulated first signal. The second modulator receives the second signal and a second modulation control signal, and generates a modulated second signal. The combiner circuit receives the modulated first signal and the modulated second signal and is configured to combine the modulated first signal and the modulated second signal to provide the phase adjusted clock signal.