Abstract: Disclosed is a method for forming a polycrystalline film. The method for forming a polycrystalline film from a film deposited on a glass substrate while a buffer layer is interposed between the deposited film and the glass substrate, which includes the steps of: preparing a mask including a transparent region having a larger size than that of resolution limitation of a laser beam equipment and an opaque region having a size which is smaller than that of the resolution limitation of the laser beam equipment; and irradiating laser beam of the maximum intensity to a film under the transparent region while irradiating the laser beam having a minimum intensity exceeding zero to the film under an opaque region by using the mask, thereby crystallizing the film by single irradiation of the laser beam.

Abstract: Disclosed is a method for forming an alignment layer of an LCD capable of preventing Mura defects when the alignment layer is formed through an LC one drop fill process. The method includes the steps of coating a mixing solution including a solvent and organic polymer materials consisting of polyimide and polyamic acid on the substrates, pre-curing the mixing solution twice with mutually different temperatures, thereby volatizing the solvent and obtaining stable phase-separation between the organic polymer materials and the solvent, and completely curing the pre-cured mixing solution at a temperature of about 180 to 240° C. A primary pre-curing process is performed at a temperature less than 50° C. under vacuum pressure of about ?35 to ?50 psi, and a secondary pre-curing process is performed at a temperature within a range of about 50 to 75° C. under the same vacuum pressure.

Abstract: Disclosed is a method for forming an alignment layer of an LCD capable of preventing Mura defects when the alignment layer is formed through an LC one drop fill process. The method includes the steps of coating a mixing solution including a solvent and organic polymer materials consisting of polyimide and polyamic acid on the substrates, pre-curing the mixing solution twice with mutually different temperatures, thereby volatizing the solvent and obtaining stable phase-separation between the organic polymer materials and the solvent, and completely curing the pre-cured mixing solution at a temperature of about 180 to 240° C. A primary pre-curing process is performed at a temperature less than 50° C. under vacuum pressure of about ?35 to ?50 psi, and a secondary pre-curing process is performed at a temperature within a range of about 50 to 75° C. under the same vacuum pressure.

Abstract: A method for forming a via hole in multiple metal layers of the semiconductor device is disclosed. In a via hole forming process of the semiconductor device, a barrier layer is formed beneath the photoresistive layer. Accordingly, the polymer residue formed on the metal-layer pattern and side wall of the via hole is prevented during the plasma etching process.

Abstract: The present invention relates to a manufacturing method of a contact of a multi-layered metal line of a highly integrated semiconductor device.The insulating layer between the metal lines is flattened and step coverage is improved by using a SOG layer or polyimide.

Abstract: A method of forming a contact region having an insulating layer which is etch protected, which includes sequentially depositing a gate oxide layer 2, a first conducting layer 3 for gate electrode, a first insulating layer 4 and a second conducting layer 5 on a silicon substrate 1. A portion of the second conducting layer 5 is etched to form an etch protective layer 5A. Portions of the etch protective layer 5A, the first insulating layer 4 and the first conducting layer 3 are sequentially etched to form separated gate electrodes 3a and 3b and separated etch protective layers 5a and 5b on the gate electrodes 3a and 3b, respectively and to expose a portion of the gate oxide layer 2 to define a source region 1A. A second insulating layer 6 is deposited on the entire surface of the resulting structure. The second insulating layer 6 is etched to form a spacer 6a on each of the side walls of the gate electrodes 3a and 3b and on the first insulating layer 4 and to expose the source region 1A.