Patents by Inventor Gon-Sub Lee
Gon-Sub Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140312266Abstract: Disclosed are a polishing slurry used in a polishing process of tungsten and a method of polishing using the same. The slurry includes an abrasive for performing polishing and an oxidation promoting agent for promoting the formation of an oxide. The abrasive includes titanium oxide particles.Type: ApplicationFiled: September 14, 2012Publication date: October 23, 2014Inventors: Jea Gun Park, Gon Sub Lee, Jin Hyung Park, Jae Hyung Lim, Jong Young Cho, Hee Sub Hwang, Hao Cui
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Patent number: 8860109Abstract: Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.Type: GrantFiled: April 30, 2009Date of Patent: October 14, 2014Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea-Gun Park, Tae-Hun Shim, Gon-Sub Lee, Seong-Je Kim, Tae-Hyun Kim
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Patent number: 8441472Abstract: Provided is a method of driving a display panel having a charge trap device and an organic light emitting diode (OLED). The charge trap device includes a nanocrystal layer. The nanocrystal layer includes nanocrystals, which are crystallized and dispersed, and a barrier layer, which buries the nanocrystals. When a program voltage is applied, charges are trapped in the nanocrystals, and the OLED emits light at a predetermined luminance with the application of a read voltage. Data signals are sequentially applied to all pixels of the display panel to express desired grayscales. The pixels of the display panel receive the read voltage and emit light at the same time.Type: GrantFiled: April 24, 2008Date of Patent: May 14, 2013Assignee: Industry-University Corporation Foundation Hanyang UniversityInventors: Jae-Gun Park, Gon-Sub Lee, Su-Hwan Lee, Sung-Ho Seo, Woo-Sik Nam, Dong-Won Shin, Dal-Ho Kim, Hyun-Min Seung, Jong-Dae Lee
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Patent number: 8315080Abstract: Provided are a luminescent device and a method of manufacturing the same. The luminescent device includes a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping layer. The charge trapping layer comprise a nanocrystal layer intervened in an organic layer, and the nanocrystal layer comprises a plurality of nanocrystals.Type: GrantFiled: April 23, 2008Date of Patent: November 20, 2012Assignee: IUCF-HYUInventors: Jea Gun Park, Gon Sub Lee, Su Hwan Lee, Dal Ho Kim, Sung Ho Seo, Woo Sik Nam, Hyun Min Seung, Jong Dae Lee, Dong Won Shin
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Publication number: 20110205217Abstract: Provided is a method of driving a display panel having a charge trap device and an organic light emitting diode (OLED). The charge trap device includes a nanocrystal layer. The nanocrystal layer includes nanocrystals, which are crystallized and dispersed, and a barrier layer, which buries the nanocrystals. When a program voltage is applied, charges are trapped in the nanocrystals, and the OLED emits light at a predetermined luminance with the application of a read voltage. Data signals are sequentially applied to all pixels of the display panel to express desired grayscales. The pixels of the display panel receive the read voltage and emit light at the same time.Type: ApplicationFiled: April 24, 2008Publication date: August 25, 2011Inventors: Jae-Gun Park, Gon-Sub Lee, Su-Hwan Lee, Sung-Ho Seo, Dong-Won Shin, Dal-Ho Kim, Hyun-Min Seung
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Publication number: 20110127580Abstract: Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.Type: ApplicationFiled: April 30, 2009Publication date: June 2, 2011Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea-Gun Park, Tae-Hun Shim, Gon-Sub Lee, Seong-Je Kim, Tae-Hyun Kim
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Publication number: 20100208507Abstract: Provided are a luminescent device and a method of manufacturing the same. The luminescent device includes a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping layer.Type: ApplicationFiled: April 23, 2008Publication date: August 19, 2010Applicant: IUCF-HYUInventors: Jea Gun Park, Gon Sub Lee, Su Hwan Lee, Dal Ho Kim, Sung Ho Seo, Woo Sik Nam, Hyun Min Seung, Jong Dae Lee, Dong Won Shin
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Publication number: 20080305574Abstract: The method of manufacturing a nonvolatile memory device includes forming a lower conductive layer on a substrate; forming a first conductive organic layer on the substrate using spin coating; forming a metal layer for forming nanocrystals on the first conductive organic layer, the metal layer partially overlapping the first conductive organic layer; forming a second conductive organic layer on the first conductive organic layer using spin coating; transforming the metal layer into nanocrystals by curing; and forming an upper conductive layer on the second conductive organic layer, the upper conductive layer partially overlapping the nanocrystals. The conductive organic polymer may be poly-N-vinylcarbazole (PVK) or polystyrene (PS).Type: ApplicationFiled: April 24, 2008Publication date: December 11, 2008Inventors: Jea-Gun Park, Gon-Sub Lee, Byeong-Il Han, Jong-Dae Lee
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Patent number: 7338882Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.Type: GrantFiled: March 21, 2005Date of Patent: March 4, 2008Assignees: Siltron Inc.Inventors: Jea-Gun Park, Gon-Sub Lee, Sang-Hee Lee
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Publication number: 20050164435Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.Type: ApplicationFiled: March 21, 2005Publication date: July 28, 2005Applicants: Park, Jea-Gun, Siltron Inc.Inventors: Jea-Gun Park, Gon-Sub Lee, Sang-Hee Lee
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Patent number: 6884694Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.Type: GrantFiled: March 19, 2003Date of Patent: April 26, 2005Assignees: Jea Gun Park, Siltron Inc.Inventors: Jea-Gun Park, Gon-Sub Lee, Sang-Hee Lee
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Publication number: 20040029358Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.Type: ApplicationFiled: March 19, 2003Publication date: February 12, 2004Inventors: Jea-Gun Park, Gon-Sub Lee, Sang-Hee Lee
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Patent number: 6472040Abstract: A silicon ingot is manufactured in a hot zone furnace by pulling the ingot from a silicon melt in the hot zone furnace in an axial direction, at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates but is sufficiently low so as to confine vacancy agglomerates to a vacancy rich region at the axis of the ingot. The ingot so pulled is sliced into a plurality of semi-pure wafers each having a vacancy rich region at the center thereof that includes vacancy agglomerates and a pure region between the vacancy rich region and the wafer edge that is free of vacancy agglomerates and interstitial agglomerates.Type: GrantFiled: December 3, 1999Date of Patent: October 29, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Jea-gun Park, Kyoo-chul Cho, Gon-sub Lee
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Patent number: 6045610Abstract: A silicon ingot is manufactured in a hot zone furnace by pulling the ingot from a silicon melt in the hot zone furnace in an axial direction, at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates but is sufficiently low so as to confine vacancy agglomerates to a vacancy rich region at the axis of the ingot. The ingot so pulled is sliced into a plurality of semi-pure wafers each having a vacancy rich region at the center thereof that includes vacancy agglomerates and a pure region between the vacancy rich region and the wafer edge that is free of vacancy agglomerates and interstitial agglomerates.Type: GrantFiled: December 12, 1997Date of Patent: April 4, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Jea-gun Park, Kyoo-chul Cho, Gon-sub Lee
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Patent number: 5980720Abstract: Methods of treating wafers for analyzing defects present therein comprise providing wafers having front side surfaces comprising defective portions and a back side surfaces opposite thereto; and decorating the defective portion of the front side of the wafer with copper.Type: GrantFiled: November 24, 1997Date of Patent: November 9, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-min Park, Jae-gun Park, Gon-sub Lee, Gi-jung Kim
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Patent number: 5944889Abstract: With a view to optimizing the donor killing process performed in the semiconductor wafer fabricating process, a heat-treating operation is performed in a thermal furnace above at least 900 .degree. C. for a predetermined time so that growth of the initial oxygen precipitates, induced into the crystal lattices during single-crystal growth, is suppressed.Type: GrantFiled: November 26, 1997Date of Patent: August 31, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-guen Park, Gon-sub Lee, Kyoo-chul Cho, Ho-kyoon Chung