Abstract: A compact and stable interferometer is easily built only with fusion splices. The air-holes of a microstructured fiber are intentionally collapsed in the vicinity of the splices and this broadens the propagating optical mode, allowing coupling from core to cladding modes. The transmission spectrum is sinusoidal and of single frequency, indicating predominant interference between the fundamental core mode (7) and a cladding mode (6). A regular interference spectrum can be observed from 650 nm to 1600 nm with fringe visibility reaching 80%. The fringe spacing is inversely proportional to the distance between the splices. This behavior has a significant impact in optical sensing and communications and so the interferometer can be applied for strain sensing. The device comprises two splices (5) of a microstructured optical fiber (1), said splices (5) determining two regions in which the air-holes (4) are collapsed, separated a length (L) along which said two modes are excited.

Abstract: A compact and stable interferometer is easily built only with fusion splices. The air-holes of a microstructured fiber are intentionally collapsed in the vicinity of the splices and this broadens the propagating optical mode, allowing coupling from core to cladding modes. The transmission spectrum is sinusoidal and of single frequency, indicating predominant interference between the fundamental core mode (7) and a cladding mode (6). A regular interference spectrum can be observed from 650 nm to 1600 nm with fringe visibility reaching 80%. The fringe spacing is inversely proportional to the distance between the splices. This behaviour has a significant impact in optical sensing and communications and so the interferometer can be applied for strain sensing. The device comprises two splices (5) of a microstructured optical fiber (1), said splices (5) determining two regions in which the air-holes (4) are collapsed, separated a length (L) along which said two modes are excited.

Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.

Abstract: A replacement gate process is disclosed comprising the steps of forming a dummy gate stack on a substrate, depositing a PMD layer on the substrate and polishing this PMD layer to expose the top surface of the dummy gate stack. The dummy gate stack can be removed selective to the spacers and the PMD layer. SiC is used as spacer or CMP stop layer to improve the uniformity of the PMD CMP step. SiC can also be used as etch stop layer during the etching of the contact holes or during the formation of a T-gate.

Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.

Abstract: A scaleable device concept and particularly a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. By using such shallow junctions, which are obtained using L-shaped spacers, the gate overlap is no longer dependent on the junction depth of the source/drain contact regions. Particularly the L-shaped spacers are used to locally reduce the penetration depth of the source/drain implantation in the substrate. This concept is particularly interesting for FET's having a channel length below 0.25 &mgr;m because this approach broadens the process window of the silicidation process of the source/drain contact regions. Moreover, the extension regions have to be subjected only to a limited thermal budget.

Abstract: A replacement gate process is disclosed comprising the steps of forming a dummy gate stack on a substrate, depositing a PMD layer on the substrate and polishing this PMD layer to expose the top surface of the dummy gate stack. The dummy gate stack can be removed selective to the spacers and the PMD layer. SiC is used as spacer or CMP stop layer to improve the uniformity of the PMD CMP step. SiC can also be used as etch stop layer during the etching of the contact holes or during the formation of a T-gate.

Abstract: A scaleable device concept and particularly a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. By using such shallow junctions, which are obtained using L-shaped spacers, the gate overlap is no longer dependent on the junction depth of the source/drain contact regions. Particularly the L-shaped spacers are used to locally reduce the penetration depth of the source/drain implantation in the substrate. This concept is particularly interesting for FET's having a channel length below 0.25 &mgr;m because this approach broadens the process window of the silicidation process of the source/drain contact regions. Moreover, the extension regions have to be subjected only to a limited thermal budget.