Patents by Inventor Gong Hyun SA

Gong Hyun SA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734407
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jang Won Kim, Gong Hyun Sa
  • Publication number: 20190312057
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 10, 2019
    Applicant: SK hynix Inc.
    Inventors: Hae Chan PARK, Jang Won KIM, Gong Hyun SA
  • Patent number: 10373971
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jang Won Kim, Gong Hyun Sa
  • Publication number: 20180053779
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Application
    Filed: April 14, 2017
    Publication date: February 22, 2018
    Applicant: SK hynix Inc.
    Inventors: Hae Chan PARK, Jang Won KIM, Gong Hyun SA