Abstract: A connector has data signal conductors for communicating data signals and voltage reference (power and ground) conductors for the signals' return currents. Voltage reference conductors carrying the same voltage level are coupled together at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals. Decoupling capacitors may alternatively or additionally be inserted between pairs of voltage reference conductors carrying high and low voltage levels at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals.

Abstract: A connector has data signal conductors for communicating data signals and voltage reference (power and ground) conductors for the signals' return currents. Voltage reference conductors carrying the same voltage level are coupled together at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals. Decoupling capacitors may alternatively or additionally be inserted between pairs of voltage reference conductors carrying high and low voltage levels at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals.

Abstract: A computer system having a processor and at least one peripheral has a programmable shared memory system and method that selectively dedicates a first potion of memory to use by the processor and allocates a second portion of memory to shared use by the processor and any peripherals in the system. The programmable memory architecture is implemented using a dual bus architecture having a first-bus connected to the processor and a second bus coupled to the processor by a system controller and to the peripherals by a peripheral controller. The programmable memory architecture additionally has a configuration controller coupled to each configurable memory bank in the system. Each configuration controller is additionally coupled to both the first and second buses. Under programmed control, the each configuration controller couples the associated memory to either the first or second bus, responsive to configuration information stored in the system controller.

Abstract: A condition sensing capacitor (10) is placed in an appropriate position such that its capacitance Cx varies in accordance with a condition to be sensed. A reference capacitor (12) and a feedback capacitor (14) are positioned in locations in which their capacitances Co and Cf are unaffected by the sensed condition. During a first time period, the sensing capacitor is connected with a source (22) of a first calibration voltage source Vg, the reference capacitor is connected with a source (26) of a second calibration voltage Vo and the feedback capacitor is connected with the output (34). During a second time period, the charge stored on the sensing capacitor is reduced by a current mirror (60) in proportion to the charge stored on the reference capacitor. The charge on the feedback capacitor is reduced by a current mirror (62) in accordance with charge stored in stray capacitance.

Abstract: There is provided an improvement in a pulsating radiation detector system comprising means in a series circuit for emitting radiation in pulses of a selected, adjusted frequency, means responsive to pulses of radiation at the frequency for creating a control signal related to the received radiation and a driving circuit for pulsating the radiation emitting means in the series circuit. The improvement comprises a modification of the driving circuit to produce voltage pulses in the series circuit at a time base width less than the reciprocal of the frequency (in seconds), with means for sensing current flow in the series circuit, means for limiting current flow in the series circuit and means for adjusting the pulse width continuously as an inverse function of the sensed circuit whereby short distinct pulses can be created for better discrimination and accuracy in the detector system.