Patents by Inventor Gong Lei
Gong Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11917237Abstract: An access point for a home network is provided. The access point includes a processor circuit. When executing software, the processor circuit is configured to receive media stream data from a media source external to the access point. Further, the processor circuit is configured to generate output data for a display device based on the received media stream data. The access point also includes an output interface for connecting to the display device. The output interface is configured to output the output data.Type: GrantFiled: February 4, 2021Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Li-Gong Kao, Chuan Hua Lei
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Patent number: 10461757Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.Type: GrantFiled: December 29, 2016Date of Patent: October 29, 2019Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Patent number: 10396805Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.Type: GrantFiled: August 31, 2018Date of Patent: August 27, 2019Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Yifan Gu, Hung-Yi Lee, Mamatha Deshpande, Shou-Po Shih, Miao Liu
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Publication number: 20180375522Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.Type: ApplicationFiled: August 31, 2018Publication date: December 27, 2018Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Yifan Gu, Hung-Yi Lee, Mamatha Deshpande, Shou-Po Shih, Miao Liu
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Patent number: 10122348Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.Type: GrantFiled: March 30, 2016Date of Patent: November 6, 2018Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Patent number: 10116470Abstract: An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.Type: GrantFiled: October 28, 2015Date of Patent: October 30, 2018Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Hungyi Lee, Yifan Gu, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Patent number: 10097190Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.Type: GrantFiled: December 29, 2016Date of Patent: October 9, 2018Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Yifan Gu, Hung-Yi Lee, Mamatha Deshpande, Shou-Po Shih, Miao Liu
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Publication number: 20180175865Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.Type: ApplicationFiled: December 29, 2016Publication date: June 21, 2018Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Yifan Gu, Hung-Yi Lee, Mamatha Deshpande, Shou-Po Shih, Miao Liu
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Patent number: 9964832Abstract: An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.Type: GrantFiled: May 28, 2015Date of Patent: May 8, 2018Assignee: Futurewei Technologies, Inc.Inventors: Morgan Chen, Yifan Gu, Hungyi Lee, Liang Gu, Yen Dang, Gong Lei, Yuming Cao, Xiao Shen, Yu Sheng Bai
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Patent number: 9941958Abstract: An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (?).Type: GrantFiled: December 15, 2015Date of Patent: April 10, 2018Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Yifan Gu, Hungyi Lee, Gong Lei, Yen Dang, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Patent number: 9838239Abstract: An apparatus comprising a first electrical driver configured to generate a first binary voltage signal according to first data, a second electrical driver configured to generate a second binary voltage signal according to second data, wherein the first data and the second data are different, and a first optical waveguide arm coupled to the first electrical driver and the second electrical driver, wherein the first optical waveguide arm is configured to shift a first phase of a first optical signal propagating along the first optical waveguide arm according to a first voltage difference between the first binary voltage signal and the second binary voltage signal to produce a first multi-level phase-shifted optical signal.Type: GrantFiled: January 7, 2016Date of Patent: December 5, 2017Assignee: Futurewei Technologies, Inc.Inventors: Morgan Chen, Qianfan Xu, Hungyi Lee, Yifan Gu, Liang Gu, Yen Dang, Gong Lei, Yuming Cao, Xiao Shen, Yu Sheng Bai
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Publication number: 20170288652Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.Type: ApplicationFiled: March 30, 2016Publication date: October 5, 2017Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Publication number: 20170170894Abstract: An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (?).Type: ApplicationFiled: December 15, 2015Publication date: June 15, 2017Inventors: Liang Gu, Yuming Cao, Yifan Gu, Hungyi Lee, Gong Lei, Yen Dang, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Publication number: 20170126443Abstract: An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.Type: ApplicationFiled: October 28, 2015Publication date: May 4, 2017Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Hungyi Lee, Yifan Gu, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Publication number: 20170126236Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.Type: ApplicationFiled: December 29, 2016Publication date: May 4, 2017Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Patent number: 9584303Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.Type: GrantFiled: October 28, 2015Date of Patent: February 28, 2017Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Publication number: 20160352325Abstract: An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.Type: ApplicationFiled: May 28, 2015Publication date: December 1, 2016Inventors: Morgan Chen, Yifan Gu, Hungyi Lee, Liang Gu, Yen Dang, Gong Lei, Yuming Cao, Xiao Shen, Yu Sheng Bai
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Publication number: 20160218811Abstract: An apparatus comprising a first electrical driver configured to generate a first binary voltage signal according to first data, a second electrical driver configured to generate a second binary voltage signal according to second data, wherein the first data and the second data are different, and a first optical waveguide arm coupled to the first electrical driver and the second electrical driver, wherein the first optical waveguide arm is configured to shift a first phase of a first optical signal propagating along the first optical waveguide arm according to a first voltage difference between the first binary voltage signal and the second binary voltage signal to produce a first, multi-level phase-shifted optical signal.Type: ApplicationFiled: January 7, 2016Publication date: July 28, 2016Inventors: Morgan Chen, Qianfan Xu, Hungyi Lee, Yifan Gu, Liang Gu, Yen Dang, Gong Lei, Yuming Cao, Xiao Shen, Yu Sheng Bai
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Patent number: 8599056Abstract: An embodiment of the present invention provides a digital-to-analog converter including: a primary modulator; a secondary modulator, connected to the primary modulator; a delay unit, connected to the primary modulator; a subtractor, connected to the delay unit and the secondary modulator separately; a first processing module, configured to perform decoding, dynamic matching, and digital-to-analog conversion in sequence on a B-bit digital signal output by the secondary modulator, so as to obtain a first analog signal; a second processing module, configured to perform decoding, dynamic matching, and digital-to-analog conversion in sequence on an (N?B+1) -bit quantization noise signal output by the subtractor, so as to obtain an analog noise signal; and an adder, connected to the first processing module and the second processing module separately, and configured to add the first analog signal and the analog noise signal, so as to obtain and output a second analog signal.Type: GrantFiled: December 27, 2012Date of Patent: December 3, 2013Assignee: Huawei Technologies Co., Ltd.Inventors: Shubao Guo, Jun Chen, Gong Lei, Yongping Liu
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Patent number: 7400284Abstract: A circuit including a first element sampling noise from and discharging noise to a signal line in response to an input signal transitioning on selected edges of a clock signal. A second element samples noise from and discharges noise to the signal line in response to another input signal transitioning on other edges of the clock signal differing from the selected edges of the clock signal such that noise coupled into substrate and supply are independent of the input signal.Type: GrantFiled: March 29, 2004Date of Patent: July 15, 2008Assignee: Cirrus Logic, Inc.Inventors: Tom Gong Lei, Bruce Eliot Duewer, Stephen Timothy Hodapp