Patents by Inventor Gongbai Cao
Gongbai Cao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923254Abstract: The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze.Type: GrantFiled: January 29, 2021Date of Patent: March 5, 2024Assignee: Zing Semiconductor CorporationInventors: Gongbai Cao, Liying Liu, Chihhsin Lin, Dengyong Yu
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Publication number: 20240071839Abstract: The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Applicant: Zing Semiconductor CorporationInventors: Gongbai CAO, Liying LIU, Chihhsin LIN, Dengyong YU
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Publication number: 20230326809Abstract: The present invention provides standard wafers, a method of making the same and a calibration method. The method of making a standard wafer comprise providing a silicon substrate having a first conductive type; forming a reverse epitaxy layer having a second conductive type; forming a target epitaxy layer having the first conductive type; measuring a measurement of a resistivity of the target epitaxy layer with four point probing, the measurement being utilized as a standard resistivity of the standard wafer.Type: ApplicationFiled: December 14, 2022Publication date: October 12, 2023Applicant: Zing Semiconductor CorporationInventors: Gongbai CAO, Shuai PAN
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Patent number: 11562917Abstract: The invention provides a method for positioning a wafer and a semiconductor manufacturing apparatus, which are applied to thin film processes. The method includes: Step S1: Obtain the state distribution of the first surface of the first wafer after the thin film process is performed on the first wafer, wherein the first surface is the surface opposite to a surface that the thin film formed thereon in the thin film process; Step S2: Determine whether the first wafer is located at the ideal positioning center according to the state distribution of the first surface, when the first wafer is not located at the ideal positioning center, according to the state distribution of the first surface adjusts the positioning position of the second wafer to be subjected to the thin film process, so that the second wafer is positioned at the ideal positioning center during the thin film process.Type: GrantFiled: December 28, 2020Date of Patent: January 24, 2023Assignee: Zing Semiconductor CorporationInventors: Liying Liu, Gongbai Cao, Chihhsin Lin
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Publication number: 20220115274Abstract: The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze.Type: ApplicationFiled: January 29, 2021Publication date: April 14, 2022Applicant: Zing Semiconductor CorporationInventors: Gongbai CAO, Liying LIU, Chihhsin LIN, Dengyong YU
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Publication number: 20220028732Abstract: The present application provides a process for preparing an epitaxy wafer, and an epitaxy wafer prepared therefrom. The process comprises: step S1: providing a semiconductor substrate wafer, conducting an epitaxy process and forming an epitaxy layer on the wafer; and step S2: conducting a thermal treatment to the wafer to eliminate the haze pattern of the epitaxy layer. According to the process, the thermal treatment after the epitaxy process can facilitate the orientation of atoms on the wafer surface toward the lowest energy orientation, so that the atoms of the epitaxy layer arrange and accumulate uniformly. Therefore, the haze pattern on the wafer surface can be eliminated.Type: ApplicationFiled: December 16, 2020Publication date: January 27, 2022Applicant: Zing Semiconductor CorporationInventors: Huajie Wang, Gongbai Cao, Chihhsin Lin
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Publication number: 20210335637Abstract: The invention provides a method for positioning a wafer and a semiconductor manufacturing apparatus, which are applied to thin film processes. The method includes: Step S1: Obtain the state distribution of the first surface of the first wafer after the thin film process is performed on the first wafer, wherein the first surface is the surface opposite to a surface that the thin film formed thereon in the thin film process; Step S2: Determine whether the first wafer is located at the ideal positioning center according to the state distribution of the first surface, when the first wafer is not located at the ideal positioning center, according to the state distribution of the first surface adjusts the positioning position of the second wafer to be subjected to the thin film process, so that the second wafer is positioned at the ideal positioning center during the thin film process.Type: ApplicationFiled: December 28, 2020Publication date: October 28, 2021Applicant: Zing Semiconductor CorporationInventors: Liying Liu, Gongbai Cao, Chihhsin Lin
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Publication number: 20210043442Abstract: The present invention provides a method for improving semiconductor thin film flatness, the method comprises providing a wafer; performing a vapor phase deposition to from an epitaxial layer on the wafer; wherein a gas suppresses epitaxial layer growth is added during the vapor phase deposition in order to tune the thickness of the epitaxial layer on the wafer edge to improve flatness of the epitaxial layer. The vapor phase deposition of the present invention can improve the flatness of the epitaxial layer on the wafer edge by adding gases which suppress epitaxial layer growth to tune the thickness of the epitaxial layer on the wafer edge, therefore, the topography of the wafer is improved as well as the SFQR values are decreased.Type: ApplicationFiled: July 14, 2020Publication date: February 11, 2021Inventors: Chenhua Dong, Chihhsin Lin, Gongbai Cao
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Publication number: 20200347513Abstract: This application provides an epitaxial wafer processing method, the processing method comprises providing an epitaxial wafer; measuring the flatness of the epitaxial wafer; performing vapor phase etching for the epitaxial wafer not meet the standard; growing epitaxial layer on the epitaxial wafer after the vapor phase etching. Compared with the traditional polishing rework process, the vapor phase etching for the epitaxial wafer of this application is much simpler and faster, therefore it can improve the production yield.Type: ApplicationFiled: April 6, 2020Publication date: November 5, 2020Inventors: Huajie Wang, Lu Fei, Gongbai Cao, Chihhsin Lin
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Patent number: 9299556Abstract: A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.Type: GrantFiled: December 31, 2010Date of Patent: March 29, 2016Assignees: SHANGHAI SIMGUI TECHNOLOGY CO. LTD., SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCESInventors: Xing Wei, Zhongdang Wang, Fei Ye, Gongbai Cao, Chenglu Lin, Miao Zhang, Xi Wang
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Publication number: 20130273714Abstract: A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.Type: ApplicationFiled: December 31, 2010Publication date: October 17, 2013Applicant: Shanghai Simgui Technology Co., Ltd.Inventors: Xing Wei, Zhongdang Wang, Fei Ye, Gongbai Cao, Chenglu Lin, Miao Zhang, Xi Wang