Patents by Inventor Gongda Yao
Gongda Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050208767Abstract: We have discovered a method of providing a thin, approximately from about 2 ? to about 100 ? thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 ??cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface to form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.Type: ApplicationFiled: February 28, 2005Publication date: September 22, 2005Inventors: Peijun Ding, Zheng Xu, Hong Zhang, Xianmin Tang, Praburam Gopalraja, Suraj Rengarajan, John Forster, Jianming Fu, Tony Chiang, Gongda Yao, Fusen Chen, Barry Chin, Gene Kohara
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Patent number: 6939801Abstract: A method to selectively deposit a barrier layer on dielectric material that surrounds one or more metal interconnects on a substrate is disclosed. The barrier layer is selectively deposited on the metal film using a cyclical deposition process including a predetermined number of deposition cycles followed by a purge step. Each deposition cycle comprises alternately adsorbing a refractory metal-containing precursor and a reducing gas on the dielectric material formed on the substrate in a process chamber.Type: GrantFiled: December 13, 2002Date of Patent: September 6, 2005Assignee: Applied Materials, Inc.Inventors: Hua Chung, Ling Chen, Vincent W. Ku, Michael X. Yang, Gongda Yao
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Patent number: 6919275Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.Type: GrantFiled: March 8, 2004Date of Patent: July 19, 2005Assignee: Applied Materials, Inc.Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
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Patent number: 6908865Abstract: Generally, a method for pre-cleaning native oxides and other contaminants from apertures on a substrate is provided. In one embodiment, a method for pre-cleaning apertures on a substrate includes disposing the substrate on a support member in a process chamber, cooling the substrate at least to a temperature of 100 degrees Celsius, and exposing the substrate to a pre-clean process. In another embodiment, a method for pre-cleaning apertures on a substrate includes cooling the substrate at least to a temperature of 100 degrees Celsius in a first chamber, transferring the substrate to a second chamber and pre-cleaning the substrate in the second chamber while maintaining a substrate temperature of 100 degrees Celsius.Type: GrantFiled: December 12, 2001Date of Patent: June 21, 2005Assignee: Applied Materials, Inc.Inventors: Martin Kranz, Srinivas Guggilla, Suraj Rengarajan, Mei Chang, Gongda Yao, Nitin Khurana, Gilbert Hausmann
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Publication number: 20050085068Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper.Type: ApplicationFiled: November 3, 2004Publication date: April 21, 2005Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen Chen, Barry Chin, Gene Kohara, Zheng Xu, Hong Zhang
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Publication number: 20050020080Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper.Type: ApplicationFiled: August 18, 2004Publication date: January 27, 2005Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen Chen, Barry Chin, Gene Kohara, Zheng Xu, Hong Zhang
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Publication number: 20040171250Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper.Type: ApplicationFiled: March 8, 2004Publication date: September 2, 2004Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
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Patent number: 6758947Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.Type: GrantFiled: June 20, 2001Date of Patent: July 6, 2004Assignee: Applied Materials, Inc.Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
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Publication number: 20030224578Abstract: A method to selectively deposit a barrier layer on dielectric material that surrounds one or more metal interconnects on a substrate is disclosed. The barrier layer is selectively deposited on the metal film using a cyclical deposition process including a predetermined number of deposition cycles followed by a purge step. Each deposition cycle comprises alternately adsorbing a refractory metal-containing precursor and a reducing gas on the dielectric material formed on the substrate in a process chamber.Type: ApplicationFiled: December 13, 2002Publication date: December 4, 2003Inventors: Hua Chung, Ling Chen, Vincent W. Ku, Michael X. Yang, Gongda Yao
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Publication number: 20030131458Abstract: An apparatus and method for processing semiconductor wafers is provided. The apparatus comprises a first buffer chamber having a first robot and a second buffer chamber having a second robot. At least one load lock is coupled to the first buffer chamber and the second buffer chamber where the first and second robots can access at least one of said load locks. A plurality of process chambers are disposed about the first and second buffer chambers.Type: ApplicationFiled: January 15, 2002Publication date: July 17, 2003Applicant: Applied Materials, Inc.Inventors: Hougong Wang, Gongda Yao, Zheng Xu
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Publication number: 20030062333Abstract: Generally, a method for pre-cleaning native oxides and other contaminants from apertures on a substrate is provided. In one embodiment, a method for pre-cleaning apertures on a substrate includes disposing the substrate on a support member in a process chamber, cooling the substrate at least to a temperature of 100 degrees Celsius, and exposing the substrate to a pre-clean process. In another embodiment, a method for pre-cleaning apertures on a substrate includes cooling the substrate at least to a temperature of 100 degrees Celsius in a first chamber, transferring the substrate to a second chamber and pre-cleaning the substrate in the second chamber while maintaining a substrate temperature of 100 degrees Celsius.Type: ApplicationFiled: December 12, 2001Publication date: April 3, 2003Applicant: Applied Materials, Inc.Inventors: Martin Kranz, Srinivas Guggilla, Suraj Rengarajan, Mei Chang, Gongda Yao, Nitin Khurana, Gilbert Hausmann
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Patent number: 6528180Abstract: A method for metallizing integrated circuits is disclosed. In one aspect, an integrated circuit is metallized by depositing liner material on a substrate followed by one or more metal layers. The liner material is selected from the group of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof. The liner material is preferably conformably deposited on the substrate using physical vapor deposition (PVD). The one or more metal layers are deposited on the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of both CVD and PVD.Type: GrantFiled: May 23, 2000Date of Patent: March 4, 2003Assignee: Applied Materials, Inc.Inventors: Wei Ti Lee, Ted Guo, Gongda Yao
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Publication number: 20020192948Abstract: A method of forming a composite barrier layer structure for use in integrated circuits is disclosed. The composite barrier layer structure formed using both physical vapor deposition (PVD) and chemical vapor deposition (CVD) techniques. The composite barrier layer structure comprises a CVD deposited layer formed on a PVD deposited layer. During the PVD process, the underlying surface of the substrate is treated, reducing the resistivity of the barrier layer structure formed thereon.Type: ApplicationFiled: June 15, 2001Publication date: December 19, 2002Applicant: Applied Materials, Inc.Inventors: Fusen Chen, Ling Chen, Gongda Yao, Ming Xi, Barry Chin, Mei Chang, Seshadri Ganguli, Michael X. Yang, Hyungsuk Alexander Yoon
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Publication number: 20020142589Abstract: Provided herein is a method of depositing alpha-tantalum film on a semiconductor wafer by depositing a tantalum nitride film on a wafer; and then depositing a tantalum film over the tantalum nitride film using wafer bias. The tantalum film as deposited is in alpha phase. Also provided is a method of depositing Cu barrier and seed layer on a semiconductor wafer, comprising the steps of depositing a tantalum nitride layer on a wafer; depositing a tantalum layer over the tantalum nitride layer using wafer bias, wherein the resulting tantalum barrier layer is in alpha phase; and then depositing Cu seed layer over the alpha-tantalum barrier layer. Further provided is a method of depositing alpha-tantalum film/layer using two-chamber process, wherein the tantalum nitride and subsequently deposited tantalum films/layers can be deposited in two separate chambers, such as IMP or SIP chambers. Still further provided is a method of depositing alpha-tantalum film by depositing PVD tantalum film on CVD films.Type: ApplicationFiled: January 31, 2001Publication date: October 3, 2002Applicant: Applied Materials, Inc.Inventors: Arvind Sundarrajan, Suraj Rengarajan, Michael A. Miller, Peijun Ding, Gongda Yao, Christophe Marcadal, Ling Chen
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Patent number: 6451179Abstract: Increased sidewall coverage in a wetting layer for a substrate via or trench is achieved in an inductively coupled plasma chamber by sputtering relatively pure aluminum.Type: GrantFiled: January 30, 1997Date of Patent: September 17, 2002Assignee: Applied Materials, Inc.Inventors: Zheng Xu, Gongda Yao
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Patent number: 6383915Abstract: We have discovered particular wetting layer or wetting/barrier layer structures which enable depositing of overlying aluminum interconnect layers having <111> texturing sufficient to provide a Rocking Curve FWHM angle &thgr; of about 1° or less. The aluminum interconnect layer exhibiting a Rocking Curve FWHM angle &thgr; of about 1° or less exhibits excellent electromigration properties. In addition when the aluminum layer is subsequently pattern etched, the sidewalls of the etched aluminum pattern exhibit a surprising reduction in pitting compared with pattern etched aluminum layers exhibiting higher Rocking Curve FWHM angles.Type: GrantFiled: February 3, 1999Date of Patent: May 7, 2002Assignee: Applied Materials, Inc.Inventors: Jingang Su, Gongda Yao, Zhang Xu, Fusen Chen
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Patent number: 6368880Abstract: The present invention provides an effective barrier layer for improved via fill in high aspect ratio sub-micron apertures at low temperature, particularly at the contact level on a substrate. In one aspect of the invention, a feature is filled by first depositing a barrier layer onto a substrate having high aspect ratio contacts or vias formed thereon. The barrier layer is preferably comprised of Ta, TaNx, W, WNx, or combinations thereof. A CVD conformal metal layer is then deposited over the barrier layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal layer is deposited onto the previously formed CVD conformal metal layer at a temperature below that of the melting point temperature of the metal to allow flow of the CVD conformal layer and the PVD metal layer into the vias.Type: GrantFiled: February 14, 2001Date of Patent: April 9, 2002Assignee: Applied Materials, Inc.Inventors: Shri Singhvi, Suraj Rengarajan, Peijun Ding, Gongda Yao
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Publication number: 20020029958Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper.Type: ApplicationFiled: June 20, 2001Publication date: March 14, 2002Applicant: Applied Materials, Inc.Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
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Patent number: 6303994Abstract: A method and apparatus are provided for reducing and eliminating the First Wafer Effect. Specifically, in a method, or system that employs a separate hot chamber for hot deposition of material that may result in the First Wafer Effect (FWE material), a cold layer of the FWE material is deposited within the hot deposition chamber prior to deposition of the hot FWE material layer.Type: GrantFiled: June 13, 2000Date of Patent: October 16, 2001Assignee: Applied Materials, Inc.Inventors: Hougong Wang, Gongda Yao
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Patent number: 6299689Abstract: A method and apparatus for reflowing a material layer is provided. The inventive method introduces into a reflow chamber a material which is at least as reactive or more reactive than a material to be reflowed (i.e., a gettering material). Preferably the gettering material is sputter deposited within the reflow chamber while a shield prevents the gettering material from reaching the material layer to be reflowed. The shield may be coupled to, or integral with a clamp for clamping a wafer (containing the material layer to be reflowed) to a wafer support provided sufficient venting exists so that contaminants degassed from the wafer may flow to the region between the sputtering target and the shield where the contaminants can react with gettering material.Type: GrantFiled: March 13, 2000Date of Patent: October 9, 2001Assignee: Applied Materials, Inc.Inventors: Hougong Wang, Steve Lai, Gongda Yao, Peijun Ding