Abstract: A class D amplifier and a method of pulse width modulation are provided. The class D amplifier includes a sigma delta modulator, a reference signal generator, a pulse width modulator and an amplifier. The sigma delta modulator converts an M bit input signal into N bit pulse code modulation data (M and N are integers and M>N). The reference signal generator counts a system clock and generates an N bit reference signal having 2N data blocks in a sampling period of the pulse code modulation data. The pulse width modulator generates a plurality of pulse width modulation signals having at least two switching periods within the sampling period of the pulse code modulation data. The pulse width modulation signals have pulse widths varied based on a unit time interval of the reference signal. The unit time interval corresponds to one of the data blocks of the reference signal.

Abstract: A class-D power amplifier, which prevents excessive response phenomenon from occurring when returning to a steady state from an abnormal state and an amplification method of the class-D power amplifier are provided. The class-D power amplifier prevents an integral control circuit or a proportional integral control circuit from becoming saturated by using sub-negative feedback loop operations, without using a high-capacity output blocking switch in an initial state or an abnormal state. Thus, suppressing pop noise due to the excessive response phenomenon caused when the class-D power amplifier returns to the steady state from the initial state or the abnormal state and reducing power consumption.

Abstract: A circuit for handling pulse width modulation (PWM) first signal and PWM second signal for outputting to an amplifier, the PWM first signal having one of a same phase and an opposite phase relationship with the PWM second signal, the circuit comprising a power detector for detecting power turn on to the amplifier and outputting a power on signal and detecting a power turn off to the amplifier and outputting a power off signal; a pulse generator having: a duty cycle generator for generating a first pulse signal corresponding to the PWM first signal and a second pulse signal corresponding to the PWM second signal, and a reduced-width generator for generating at least one of a reduced-width first pulse and a reduced-width second pulse; a controller for selecting one of the reduced-width first pulse and the reduced-width second pulse for outputting to the amplifier upon receipt of the power on signal and for selecting the first pulse signal and the second pulse signal for outputting to the amplifier thereafter; a

Abstract: A class D amplifier and a method of pulse width modulation are provided. The class D amplifier includes a sigma delta modulator, a reference signal generator, a pulse width modulator and an amplifier. The sigma delta modulator converts an M bit input signal into N bit pulse code modulation data (M and N are integers and M>N). The reference signal generator counts a system clock and generates an N bit reference signal having 2N data blocks in a sampling period of the pulse code modulation data. The pulse width modulator generates a plurality of pulse width modulation signals having at least two switching periods within the sampling period of the pulse code modulation data. The pulse width modulation signals have pulse widths varied based on a unit time interval of the reference signal. The unit time interval corresponds to one of the data blocks of the reference signal.

Abstract: Disclosed is a digital PWM input D class amplifier by PWM negative feedback. The amplifier includes: digital modulation part for modulating PCM signal of input audio to PWM signal; pulse width generating and correcting part for comparing difference between the PWM signal and output signal negatively fed back, with PWM ramp signal to generate PWM switching signal; output part for generating an amplified output audio signal in response to the PWM switching signal of the pulse width generating and correcting part; and voltage negative feedback loop for negatively feeding back signal of the output part and decreasing a harmonic component to provide the signal to the pulse width generating and correcting part. Thus, the invention compares the negative feedback signal with positive/negative (+/?) saw tooth PWM ramp signal to control On/Off time period of switching transistor and the PWM pulse width and thereby enhance the linearity of the output PWM.

Abstract: Disclosed is a digital PWM input D class amplifier by PWM negative feedback. The amplifier includes: digital modulation part for modulating PCM signal of input audio to PWM signal; pulse width generating and correcting part for comparing difference between the PWM signal and output signal negatively fed back, with PWM ramp signal to generate PWM switching signal; output part for generating an amplified output audio signal in response to the PWM switching signal of the pulse width generating and correcting part; and voltage negative feedback loop for negatively feeding back signal of the output part and decreasing a harmonic component to provide the signal to the pulse width generating and correcting part. Thus, the invention compares the negative feedback signal with positive/negative (+/?) saw tooth PWM ramp signal to control On/Off time period of switching transistor and the PWM pulse width and thereby enhance the linearity of the output PWM.

Abstract: A class-D power amplifier, which prevents excessive response phenomenon from occurring when returning to a steady state from an abnormal state and an amplification method of the class-D power amplifier are provided. The class-D power amplifier prevents an integral control circuit or a proportional integral control circuit from becoming saturated by using sub-negative feedback loop operations, without using a high-capacity output blocking switch in an initial state or an abnormal state. Thus, suppressing pop noise due to the excessive response phenomenon caused when the class-D power amplifier returns to the steady state from the initial state or the abnormal state and reducing power consumption.

Abstract: A circuit for handling pulse width modulation (PWM) first signal and PWM second signal for outputting to an amplifier, the PWM first signal having one of a same phase and an opposite phase relationship with the PWM second signal, the circuit comprising a power detector for detecting power turn on to the amplifier and outputting a power on signal and detecting a power turn off to the amplifier and outputting a power off signal; a pulse generator having: a duty cycle generator for generating a first pulse signal corresponding to the PWM first signal and a second pulse signal corresponding to the PWM second signal, and a reduced-width generator for generating at least one of a reduced-width first pulse and a reduced-width second pulse; a controller for selecting one of the reduced-width first pulse and the reduced-width second pulse for outputting to the amplifier upon receipt of the power on signal and for selecting the first pulse signal and the second pulse signal for outputting to the amplifier thereafter; a