Abstract: The present invention provides a method and a system for high performance image signal processing of continuous images in real time. The system comprising a focal plane array for generating continuous source image frames in real time. The focal plane array divided logically into blocks of sub-frames. The system also comprising an analog to digital converter (ADC) layer having an array of ADC elements for converting the source image frames into a digital data. The system further comprising a digital processor layer having an array of processing elements for processing the digital data and an interconnecting layer for connecting each one of the ADC elements and the digital processing elements substantially vertically to the focal plane and substantially parallel to one another. The processing comprising reducing image motion blur, increasing image dynamic range, increasing image depth of field and obtaining features of the images.

Abstract: A method and apparatus for optimizing image quality based on scene content comprising a sensor for generating a sequence of frames where each frame in the sequence of frames comprises content representing a scene and a digital processor, coupled to the sensor, for performing scene content analysis and for establishing a window defining a number of input frames from the sensor and processed output frames, and for aligning and combining the number of frames in the window to form an output frame, wherein sensor parameters and frame combination parameters are adjusted based on scene content.

Abstract: The present invention provides a method and a system for high performance image signal processing of continuous images in real time. The system comprising a focal plane array for generating continuous source image frames in real time. The focal plane array divided logically into blocks of sub-frames. The system also comprising an analog to digital converter (ADC) layer having an array of ADC elements for converting the source image frames into a digital data. The system further comprising a digital processor layer having an array of processing elements for processing the digital data and an interconnecting layer for connecting each one of the ADC elements and the digital processing elements substantially vertically to the focal plane and substantially parallel to one another. The processing comprising reducing image motion blur, increasing image dynamic range, increasing image depth of field and obtaining features of the images.

Abstract: A video processor that uses a low latency pyramid processing technique for fusing images from multiple sensors. The imagery from multiple sensors is enhanced, warped into alignment, and then fused with one another in a manner that provides the fusing to occur within a single frame of video, i.e., sub-frame processing. Such sub-frame processing results in a sub-frame delay between a moment of capturing the images to the display of the fused imagery.

Abstract: A pipelined parallel processor (PPP) integrated circuit includes a filtering unit, internal routing circuitry such as a crosspoint switch, an internal frame store controller, and one or more function circuits. The function circuits include, for example, arithmetic units, lookup tables, timing compensators, adders/subtractors, statistics modules, image shifting circuitry, and other useful processing devices. The components of the PPP are interconnected with the crosspoint switch that routes data among the frame store controller, filtering unit, function circuits, external input channels, and external output channels. The internal frame store controller includes a plurality of programmable video line store memories that are coupled to an external field or frame store memory. Each line store memory may be programmed to provide data to, or receive data from one of the PPP components by a controller and to transfer the data from or to the memory, respectively.

Abstract: A pipelined parallel processor (PPP) integrated circuit includes a filtering unit, internal routing circuitry such as a crosspoint switch, an internal frame store controller, and one or more function circuits. The function circuits include, for example, arithmetic units, lookup tables, timing compensators, adders/subtractors, statistics modules, image shifting circuitry, and other useful processing devices. The components of the PPP are interconnected with the crosspoint switch that routes data among the frame store controller, filtering unit, function circuits, external input channels, and external output channels. The internal frame store controller includes a plurality of programmable video line store memories that are coupled to an external field or frame store memory. Each line store memory may be programmed to provide data to, or receive data from one of the PPP components by a controller and to transfer the data from or to the memory, respectively.

Abstract: A pipelined parallel processor (PPP) integrated circuit includes a filtering unit, internal routing circuitry such as a crosspoint switch, an internal frame store controller, and one or more function circuits. The function circuits include, for example, arithmetic units, lookup tables, timing compensators, adders/subtractors, statistics modules, image shifting circuitry, and other useful processing devices. The components of the PPP are interconnected with the crosspoint switch that routes data among the frame store controller, filtering unit, function circuits, external input channels, and external output channels. The internal frame store controller includes a plurality of programmable video line store memories that are coupled to an external field or frame store memory. Each line store memory may be programmed to provide data to, or receive data from one of the PPP components by a controller and to transfer the data from or to the memory, respectively.

Abstract: A real-time modular video processing system (VPS) which can be scaled smoothly from relatively small systems with modest amounts of hardware to very large, very powerful systems with significantly more hardware. The modular video processing system includes a processing module containing at least one general purpose microprocessor which controls hardware and software operation of the video processing system using control data and which also facilitates communications with external devices. One or more video processing modules are also provided, each containing parallel pipelined video hardware which is programmable by the control data to provide different video processing operations on an input stream of video data. Each video processing module also contains one or more connections for accepting one or more daughterboards which each perform a particular image processing task.

Abstract: Digital signal processing circuitry implemented in ASICs or FPGAs is built by combining multi-component constructs (e.g. macrocells). These circuits may be modified to include a timing channel by augmenting selected ones of the constructs to include a path which propagates a timing signal with a delay that compensates for the signal processing delay through the construct. The selected constructs are those that are used in a critical processing path in the digital signal processing circuitry. A timing compensation circuit may also be defined as a construct. This block receives two digital data signals having accompanying timing signals and delays the first signal that provides valid data until the second signal also provides valid data, as determined by their timing signals. A configurable arithmetic and logic unit (ALU) made using these techniques includes a timing compensation circuit, a look-up table and an accumulator.

Abstract: A digital image warper system produces a warped output image from an input image. The warper system increases the sampling rate of a sampled image above the Nyquist rate or samples an analog image at a higher rate than the Nyquist rate and prefilters the upsampled image to counteract filtering which may occur during the warping operation. The upsampled image is warped using an interpolator for resampling to produce a warped upsampled image. The interpolator is, for example, a low quality interpolator such as a bilinear interpolator. The warped image is then down-sampled to the same resolution as the input image to produce the warped image. Down-sampling and warping can be combined into one step by modifying the geometric transformation function implemented when warping the upsampled image.

Abstract: An apparatus for assessing the visibility of differences between two input image sequences. The apparatus comprises a pair of pre-filtered processors, a pair of pyramid constructors and a JND processor. Each pre-filter processor receives a separate input image sequence and performs temporal filtering to produce a low-pass temporal response and a bandpass temporal response. In turn, the pyramid constructors receive the temporal responses and generate contrast pyramids for the temporal responses. The JND processor evaluates the contrast pyramids to produce an image metric which is used to assess the visibility of differences between the two input image sequences.