Abstract: To enhance the performance of computing arithmetic operations, where the operations can utilize the matrix multiplication process available on processing units. The matrix multiplication process can be implemented as software, a hardware unit that is part of the processing unit, or a combination thereof. Utilizing the matrix multiplication process can utilize available processing bandwidth that would ordinarily not be used for the arithmetic operation. The process can decompose the arithmetic operation to a modular multiplication operation. The modular multiplication operation can be transformed to a redundant representation. The redundant representation can be mapped to the matrix multiplication process. The result can be computed and returned to the calling thread. In some aspects, the result can be a recombination of partial redundant representations that are offset to provide the appropriate place holder values.

Abstract: Systems and methods herein secure computer memory from potential hacks. In one embodiment, a system includes a computer memory, and a memory protection module communicatively coupled to the computer memory. The memory protection module is operable to assign a counter value to a write Input/Output (I/O) request, to encrypt data of the write I/O request based on the counter value, and to write the encrypted data to a location of the computer memory. The counter value comprises a version number of the write I/O request and, for example, the location of the computer memory to where the data of the write I/O request is being written in the computer memory. The memory protection module is further operable to compute the version number based on memory access patterns of an application writing to the computer memory.

Abstract: Systems and methods herein secure computer memory from potential hacks. In one embodiment, a system includes a computer memory, and a memory protection module communicatively coupled to the computer memory. The memory protection module is operable to assign a counter value to a write Input/Output (I/O) request, to encrypt data of the write I/O request based on the counter value, and to write the encrypted data to a location of the computer memory. The counter value comprises a version number of the write I/O request and, for example, the location of the computer memory to where the data of the write I/O request is being written in the computer memory. The memory protection module is further operable to compute the version number based on memory access patterns of an application writing to the computer memory.

Abstract: Subsets of multiple signal generator circuits embodied in a device are selected, and then a volatile value for the device is generated from the selected subsets. The volatile value may be used for authentication of the device and/or for cryptographic procedures performed on the device. The signal generator circuits may each comprise an oscillator circuit, and the selection of the subsets may be according to a comparison of the outputs of the subsets of circuits, for example, according to a comparison of output oscillation frequencies.