Patents by Inventor Gopal Gudhur Karanam
Gopal Gudhur Karanam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9069689Abstract: The sampling rate of a digital signal is reduced by storing a series of partial sums of the digital signal instead of the signal itself, thus reducing the memory size required to perform the sampling-rate reduction.Type: GrantFiled: June 6, 2012Date of Patent: June 30, 2015Assignee: ANALOG DEVICES, INC.Inventors: Boris Lerner, Gopal Gudhur Karanam
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Patent number: 8947446Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: GrantFiled: May 13, 2013Date of Patent: February 3, 2015Assignee: Analog Devices TechnologyInventors: Boris Lerner, Michael Meyer-Pundsack, Gopal Gudhur Karanam, Pradip Thacker
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Patent number: 8929664Abstract: A method for identifying objects in a digital image includes tracing chain codes associated with the contour of the object; a series of states is maintained, and the next chain codes in the contour are accepted only if they comply with allowed chain codes for each state. Certain chain codes trigger a transition into a next state. If a disallowed chain code is encountered, the process halts.Type: GrantFiled: May 30, 2012Date of Patent: January 6, 2015Assignee: Analog Devices, Inc.Inventors: Bijesh Poyil, Gopal Gudhur Karanam, Ramandeep Singh Kukreja
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Patent number: 8766992Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: GrantFiled: May 13, 2013Date of Patent: July 1, 2014Assignee: Analog Devices, Inc.Inventors: Boris Lerner, Michael Meyer-Pundsack, Gopal Gudhur Karanam, Pradip Thaker
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Publication number: 20130342551Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: ApplicationFiled: May 13, 2013Publication date: December 26, 2013Applicant: ANALOG DEVICES TECHNOLOGYInventors: Boris Lerner, Michael Meyer-Pundsack, Gopal Gudhur Karanam, Pradip Thaker
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Publication number: 20130332495Abstract: The sampling rate of a digital signal is reduced by storing a series of partial sums of the digital signal instead of the signal itself, thus reducing the memory size required to perform the sampling-rate reduction.Type: ApplicationFiled: June 6, 2012Publication date: December 12, 2013Applicant: Analog Devices Inc.Inventors: BORIS LERNER, Gopal Gudhur Karanam
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Publication number: 20130322771Abstract: A method for identifying objects in a digital image includes tracing chain codes associated with the contour of the object; a series of states is maintained, and the next chain codes in the contour are accepted only if they comply with allowed chain codes for each state. Certain chain codes trigger a transition into a next state. If a disallowed chain code is encountered, the process halts.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Applicant: Analog Devices Inc.Inventors: Bijesh Poyil, Gopal Gudhur Karanam, Ramandeep Singh Kukreja
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Publication number: 20130249923Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: ApplicationFiled: May 13, 2013Publication date: September 26, 2013Applicant: ANALOG DEVICES TECHNOLOGYInventors: Michael Meyer-Pundsack, Boris Lerner, Gopal Gudhur Karanam, Pradip Thacker
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Publication number: 20130202155Abstract: A method for detecting a lane marker, the method including (i) receiving, from an image acquisition device, a first image comprising the road lane marker, (ii) scanning, into a memory, a first substantially horizontal line across the first image, (iii) computing, using a processor, an intensity gradient from the first scanned line, and (iv) determining a first position of the road lane marker by analyzing the intensity gradient.Type: ApplicationFiled: February 3, 2012Publication date: August 8, 2013Inventor: Gopal Gudhur Karanam
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Patent number: 8441492Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: GrantFiled: January 20, 2012Date of Patent: May 14, 2013Assignee: Analog Devices Inc.Inventors: Michael Meyer-Pundsack, Boris Lerner, Gopal Gudhur Karanam, Pradip Thaker
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Publication number: 20120176389Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: ApplicationFiled: January 20, 2012Publication date: July 12, 2012Applicant: Analog Devices, Inc.Inventors: Boris Lerner, Pradip Thaker, Gopal Gudhur Karanam, Michael Meyer-Pundsack
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Patent number: 8130229Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: GrantFiled: November 17, 2009Date of Patent: March 6, 2012Assignee: Analog Devices, Inc.Inventors: Boris Lerner, Pradip Thaker, Gopal Gudhur Karanam, Michael Meyer-Pundsack
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Publication number: 20110115804Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: ApplicationFiled: November 17, 2009Publication date: May 19, 2011Inventors: Boris Lerner, Pradip Thaker, Gopal Gudhur Karanam, Michael Meyer-Pundsack