Abstract: A phase locked loop circuit, system, and method of operation are provided. The phase-locked loop (PLL) includes a first PLL and a second PLL. The first PLL is nested inside the second PLL. According to one embodiment, the first PLL is coupled to the output of a surface acoustic wave (SAW) resonator, and includes first divider coupled within a feedback loop of the first PLL. The second PLL is coupled between an input of the overall PLL circuit, and output from the first PLL and the first divider. According to a second embodiment, the second PLL includes a SAW voltage-controlled oscillator (VCSO) and a second divider coupled to an output of the first PLL. Regardless of whether the first or second embodiments are contemplated, the nested first and second PLL circuits provide an agile, low phase noise, clock synthesizer and jitter attenuator hereof.

Abstract: A mixed signal method and system for tuning a voltage controlled oscillator is described. The method includes dividing a frequency range of an oscillator circuit into a plurality of regions, digitally selecting and tuning one of the plurality of regions of the divided frequency range of the oscillator circuit, and further tuning the selected region of the frequency range of the oscillator circuit via one or more analog tuning elements.